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Rev Log message Author Age Path
338 root 2054d 17h /ethmac/tags/rel_10/
335 New directory structure. root 2111d 22h /ethmac/tags/rel_10/
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 4417d 18h /ethmac/tags/rel_10/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 4417d 18h /ethmac/tags/rel_10/
245 Rev 1.7. mohor 4418d 11h /ethmac/tags/rel_10/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 4418d 14h /ethmac/tags/rel_10/
243 Late collision is not reported any more. tadejm 4418d 19h /ethmac/tags/rel_10/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 4419d 10h /ethmac/tags/rel_10/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 4419d 10h /ethmac/tags/rel_10/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 4419d 10h /ethmac/tags/rel_10/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 4419d 10h /ethmac/tags/rel_10/
238 Defines fixed to use generic RAM by default. mohor 4431d 14h /ethmac/tags/rel_10/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 4433d 19h /ethmac/tags/rel_10/
235 rev 4. mohor 4434d 10h /ethmac/tags/rel_10/
234 Figure list assed to the revision 3. mohor 4434d 18h /ethmac/tags/rel_10/
233 Revision 0.3 released. Some figures added. mohor 4434d 18h /ethmac/tags/rel_10/
232 fpga define added. mohor 4439d 13h /ethmac/tags/rel_10/
231 Description of Core Modules added (figure). mohor 4441d 15h /ethmac/tags/rel_10/
229 case changed to casex. mohor 4445d 11h /ethmac/tags/rel_10/
227 Changed BIST scan signals. tadejm 4445d 15h /ethmac/tags/rel_10/

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