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Rev Log message Author Age Path
338 root 2055d 06h /ethmac/tags/rel_1/
335 New directory structure. root 2112d 12h /ethmac/tags/rel_1/
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 4533d 05h /ethmac/tags/rel_1/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 4533d 05h /ethmac/tags/rel_1/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 4533d 05h /ethmac/tags/rel_1/
120 Unused files removed. mohor 4533d 06h /ethmac/tags/rel_1/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 4533d 06h /ethmac/tags/rel_1/
118 ShiftEnded synchronization changed. mohor 4536d 21h /ethmac/tags/rel_1/
117 Clock mrx_clk set to 2.5 MHz. mohor 4537d 08h /ethmac/tags/rel_1/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 4537d 08h /ethmac/tags/rel_1/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 4538d 06h /ethmac/tags/rel_1/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 4539d 03h /ethmac/tags/rel_1/
113 RxPointer bug fixed. mohor 4545d 19h /ethmac/tags/rel_1/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 4546d 09h /ethmac/tags/rel_1/
111 Master state machine had a bug when switching from master write to
master read.
mohor 4546d 22h /ethmac/tags/rel_1/
110 m_wb_cyc_o signal released after every single transfer. mohor 4547d 01h /ethmac/tags/rel_1/
109 Comment removed. mohor 4547d 02h /ethmac/tags/rel_1/
108 Testbench supports unaligned accesses. mohor 4614d 11h /ethmac/tags/rel_1/
107 TX_BUF_BASE changed. mohor 4614d 11h /ethmac/tags/rel_1/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 4614d 11h /ethmac/tags/rel_1/

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