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Rev Log message Author Age Path
360 Added partial implementation of the debug register from ORPSoC olof 1179d 14h /ethmac/
359 Verilator linting fixes olof 1181d 17h /ethmac/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 1183d 07h /ethmac/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 1183d 07h /ethmac/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 1183d 09h /ethmac/
355 Import Julius Baxter's verilator hints from ORPSoC olof 1183d 09h /ethmac/
354 Whitespace cleanup olof 1183d 10h /ethmac/
353 Inherit fixes for bit width of constants from ORPSoC olof 1185d 11h /ethmac/
352 Removed delayed assignments from rtl code olof 1189d 17h /ethmac/
351 Turn defines into parameters in eth_cop olof 1198d 07h /ethmac/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 1198d 08h /ethmac/
349 Make all parameters configurable from top level olof 1199d 08h /ethmac/
348 Added option to dump VCD files olof 1200d 07h /ethmac/
347 Added information about running with Icarus Verilog olof 1200d 08h /ethmac/
346 Updated project location olof 1200d 10h /ethmac/
345 Temporarily disable failing tests olof 1200d 11h /ethmac/
344 bit 9 in phy control register is self clearing olof 1206d 14h /ethmac/
343 Address miss should not be asserted on short frames olof 1210d 09h /ethmac/
342 Added cast to avoid inequality when comparing different data types olof 1210d 10h /ethmac/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 1210d 10h /ethmac/

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