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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 1109d 21h /ethmac/
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 1172d 18h /ethmac/
366 Readded eth_top.v with a deprecation warning olof 1296d 22h /ethmac/
365 Whitespace cleanup olof 1297d 21h /ethmac/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 1298d 19h /ethmac/
363 quartus project files unneback 1299d 03h /ethmac/
362 added Makefiles to build project unneback 1299d 03h /ethmac/
361 created branch unneback unneback 1299d 04h /ethmac/
360 Added partial implementation of the debug register from ORPSoC olof 1300d 02h /ethmac/
359 Verilator linting fixes olof 1302d 04h /ethmac/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 1303d 18h /ethmac/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 1303d 19h /ethmac/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 1303d 20h /ethmac/
355 Import Julius Baxter's verilator hints from ORPSoC olof 1303d 21h /ethmac/
354 Whitespace cleanup olof 1303d 22h /ethmac/
353 Inherit fixes for bit width of constants from ORPSoC olof 1305d 23h /ethmac/
352 Removed delayed assignments from rtl code olof 1310d 05h /ethmac/
351 Turn defines into parameters in eth_cop olof 1318d 19h /ethmac/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 1318d 19h /ethmac/
349 Make all parameters configurable from top level olof 1319d 20h /ethmac/

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