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Rev Log message Author Age Path
235 rev 4. mohor 4375d 23h /
234 Figure list assed to the revision 3. mohor 4376d 07h /
233 Revision 0.3 released. Some figures added. mohor 4376d 07h /
232 fpga define added. mohor 4381d 02h /
231 Description of Core Modules added (figure). mohor 4383d 04h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 4387d 00h /
229 case changed to casex. mohor 4387d 00h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 4387d 04h /
227 Changed BIST scan signals. tadejm 4387d 04h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 4387d 05h /
225 Some minor changes. tadejm 4387d 06h /
224 Signals for a wave window in Modelsim. tadejm 4387d 07h /
223 Some code changed due to bug fixes. tadejm 4387d 07h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 4391d 05h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 4391d 05h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 4394d 06h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 4394d 06h /
218 Typo error fixed. (When using Bist) mohor 4394d 08h /
217 Bist supported. mohor 4394d 08h /
216 Bist signals added. mohor 4394d 08h /

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