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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] - Rev 111

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  • Rev 111 2011-05-20 20:39:02 GMT
  • Author: olivier.girard
  • Log message:
    Re-organized the "openMSP430_defines.v" file.
    Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
    Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
    As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
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[FOLDER] openmsp430/ 111  1253d 09h olivier.girard View Log RSS feed
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[NODE][FOLDER] trunk/ 111  1253d 09h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] core/ 111  1253d 09h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] doc/ 100  1333d 09h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] fpga/ 111  1253d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] actel_m1a3pl_dev_kit/ 111  1253d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera_de1_board/ 111  1253d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx_diligent_s3board/ 111  1253d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] bench/ 111  1253d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] doc/ 2  1942d 08h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] rtl/ 111  1253d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] verilog/ 111  1253d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] sim/ 111  1253d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] software/ 106  1309d 08h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] synthesis/ 111  1253d 09h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] tools/ 110  1254d 09h olivier.girard View Log RSS feed

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