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[/] [openmsp430/] [trunk/] [core/] [sim/] - Rev 33

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  • Rev 33 2009-12-29 18:18:00 GMT
  • Author: olivier.girard
  • Log message:
    In order to avoid confusion, the following changes have been implemented to the Verilog code:
    - renamed the "rom_*" ports and defines to "pmem_*" (program memory).
    - renamed the "ram_*" ports and defines to "dmem_*" (data memory).

    In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.
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[NODE][FOLDER] trunk/ 33  1569d 03h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] core/ 33  1569d 03h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 33  1569d 03h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 2  1751d 00h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 33  1569d 03h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 33  1569d 03h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] rtl_sim/ 33  1569d 03h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] synthesis/ 2  1751d 00h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] doc/ 32  1570d 23h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] fpga/ 32  1570d 23h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] tools/ 15  1716d 01h olivier.girard View Log RSS feed

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