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[/] [openmsp430/] [trunk/] [core/] [rtl/] - Rev 106

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  • Rev 106 2011-03-25 22:01:03 GMT
  • Author: olivier.girard
  • Log message:
    Separated the Timer A defines from the openMSP430 ones.
    Added the "dbg_en" port in order to allow a separate reset of the debug interface.
    Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
    Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
    Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
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[NODE][NODE][NODE][FOLDER] bench/ 106  1339d 19h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 2  1972d 20h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 106  1339d 19h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] verilog/ 106  1339d 19h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 106  1339d 19h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] synthesis/ 73  1573d 22h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] doc/ 100  1363d 20h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] fpga/ 106  1339d 19h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] tools/ 97  1365d 21h olivier.girard View Log RSS feed

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