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<h1>Wishbone Monitor Controller VGA Chip</h1>
<h2>Description</h2>
<strong>Wishbone Monitor Controller VGA Chip</strong> adds a simple 
<a href="/cores/wb_tk/wb_async_master.shtml">asyncronous master</a>
and <a href="/cores/wb_tk/wb_async_slave.shtml">slave</a>
interface to the <a href="vga_core.shtml">VGA core</a> module.
It also resolves all generics with constants thus
before and after sythetesys simulation can be performed with the same
test-benches. It is ideal to be used with external CPUs and SRAM-based
pixel memory when there is enough address space available to directly
map the whole pixel memory to the CPUs address space. No acceleration
functions are included nor palette is incorporated. It is intended as
a DEMO application rather than a real-world example.
 
<h2>Author & Maintainer</h2>
<p>
<a href="/people/tantos">Andras Tantos</a>
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