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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [template_periph_8b.s43] - Rev 141

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                     8 BIT PERIPHERAL TEMPLATE                             */
/*---------------------------------------------------------------------------*/
/* Test the 8 bit peripheral template:                                       */
/*                                     - Read/Write register access.         */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 141 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $          */
/*===========================================================================*/

.include "pmem_defs.asm"

.global main

.set   CNTRL1, 0x0090
.set   CNTRL2, 0x0091
.set   CNTRL3, 0x0092
.set   CNTRL4, 0x0093

main:
        /* --------------     TEST RD/WR REGISTER ACCESS     --------------- */

        mov.b #0x11,   &CNTRL1         ; CNTRL1
        mov.b &CNTRL1, &DMEM_200
        mov.b #0xee,   &CNTRL1
        mov.b &CNTRL1, &DMEM_201

        mov.b #0xaa,   &CNTRL2         ; CNTRL2
        mov.b &CNTRL2, &DMEM_202
        mov.b #0x55,   &CNTRL2
        mov.b &CNTRL2, &DMEM_203

        mov.b #0x5a,   &CNTRL3         ; CNTRL3
        mov.b &CNTRL3, &DMEM_204
        mov.b #0xa5,   &CNTRL3
        mov.b &CNTRL3, &DMEM_205

        mov.b #0x55,   &CNTRL4         ; CNTRL4
        mov.b &CNTRL4, &DMEM_206
        mov.b #0xaa,   &CNTRL4
        mov.b &CNTRL4, &DMEM_207

        
        mov   #0x0001, r15



        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff


        /* ----------------------         INTERRUPT VECTORS  --------------- */

.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    <unused>
.word end_of_test  ; Interrupt  1                      <unused>
.word end_of_test  ; Interrupt  2                      <unused>
.word end_of_test  ; Interrupt  3                      <unused>
.word end_of_test  ; Interrupt  4                      <unused>
.word end_of_test  ; Interrupt  5                      <unused>
.word end_of_test  ; Interrupt  6                      <unused>
.word end_of_test  ; Interrupt  7                      <unused>
.word end_of_test  ; Interrupt  8                      <unused>
.word end_of_test  ; Interrupt  9                      <unused>
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      <unused>
.word end_of_test  ; Interrupt 12                      <unused>
.word end_of_test  ; Interrupt 13                      <unused>
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

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