Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] [msp430sim] - Rev 2
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#!/bin/sh#------------------------------------------------------------------------------# Copyright (C) 2001 Authors## This source file may be used and distributed without restriction provided# that this copyright statement is not removed from the file and that any# derivative work contains the original copyright notice and the associated# disclaimer.## This source file is free software; you can redistribute it and/or modify# it under the terms of the GNU Lesser General Public License as published# by the Free Software Foundation; either version 2.1 of the License, or# (at your option) any later version.## This source is distributed in the hope that it will be useful, but WITHOUT# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public# License for more details.## You should have received a copy of the GNU Lesser General Public License# along with this source; if not, write to the Free Software Foundation,# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA##------------------------------------------------------------------------------## File Name: msp430sim##------------------------------------------------------------------------------################################################################################ Parameter Check ################################################################################EXPECTED_ARGS=1if [ $# -ne $EXPECTED_ARGS ]; thenecho "ERROR : wrong number of arguments"echo "USAGE : msp430sim <test name>"echo "Example : msp430sim c-jump_jge"exit 1fi################################################################################ Check if the required files exist ################################################################################asmfile=../src/$1.s43;verfile=../src/$1.v;submitfile=../src/submit.f;incfile=../../../rtl/verilog/openMSP430.inc;deffile=../bin/template.def;if [ ! -e $asmfile ]; thenecho "Assembler file $asmfile doesn't exist: $asmfile"exit 1fiif [ ! -e $verfile ]; thenecho "Verilog stimulus file $verfile doesn't exist: $verfile"exit 1fiif [ ! -e $submitfile ]; thenecho "Verilog submit file $submitfile doesn't exist: $submitfile"exit 1fiif [ ! -e $deffile ]; thenecho "Linker definition file template doesn't exist: $deffile"exit 1fi################################################################################ Cleanup ################################################################################echo "Cleanup..."rm -rf rom.*rm -rf stimulus.v################################################################################ Run simulation ################################################################################echo " ======================================================="echo "| Start simulation: $1"echo " ======================================================="# Create linksln -s $asmfile rom.s43ln -s $verfile stimulus.v# Make local copy of the openMSP403 configuration file and remove commentscp $incfile ./rom.incsed -i "/^\/\// s,.*,," rom.inc# Get ROM sizeromsize=`grep ROM_AWIDTH rom.inc | grep -v ROM_MSB | grep -v ROM_SIZE`romsize=${romsize##* }romsize=$((2<<$romsize))# Get RAM sizeramsize=`grep RAM_AWIDTH rom.inc | grep -v RAM_MSB | grep -v RAM_SIZE`ramsize=${ramsize##* }ramsize=$((2<<$ramsize))# Compile assembler codeecho "Compile, link & generate IHEX file (ROM: $romsize B, RAM: $ramsize B)..."../bin/asm2ihex.sh rom rom.s43 $deffile $romsize $ramsize# Generate ROM memory fileecho "Convert IHEX file to Verilog MEMH format..."../bin/ihex2mem.tcl -ihex rom.ihex -out rom.mem -mem_size $romsize# Start verilog simulationecho "Start Verilog simulation..."../bin/rtlsim.sh stimulus.v rom.mem $submitfile
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