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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [periph/] [omsp_gpio.v] - Diff between revs 37 and 79

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Rev 37 Rev 79
Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 37 $
// $Rev: 79 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
// $LastChangedDate: 2010-11-23 20:36:16 +0100 (Tue, 23 Nov 2010) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`include "timescale.v"
`include "timescale.v"
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
 
 
module  omsp_gpio (
module  omsp_gpio (
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// 3) REGISTERS
// 3) REGISTERS
//============================================================================
//============================================================================
 
 
// P1IN Register
// P1IN Register
//---------------
//---------------
 
reg  [7:0] p1in_s;
reg  [7:0] p1in;
reg  [7:0] p1in;
 
 
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc)
  if (puc)  p1in <=  8'h00;
  if (puc)
  else      p1in <=  p1_din & P1_EN_MSK;
    begin
 
       p1in_s <=  8'h00;
 
       p1in   <=  8'h00;
 
    end
 
  else
 
    begin
 
       p1in_s <=  p1_din & P1_EN_MSK;
 
       p1in   <=  p1in_s & P1_EN_MSK;
 
    end
 
 
 
 
// P1OUT Register
// P1OUT Register
//----------------
//----------------
reg  [7:0] p1out;
reg  [7:0] p1out;
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assign p1_sel = p1sel;
assign p1_sel = p1sel;
 
 
 
 
// P2IN Register
// P2IN Register
//---------------
//---------------
 
reg  [7:0] p2in_s;
reg  [7:0] p2in;
reg  [7:0] p2in;
 
 
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc)
  if (puc)      p2in <=  8'h00;
  if (puc)
  else          p2in <=  p2_din & P2_EN_MSK;
    begin
 
       p2in_s <=  8'h00;
 
       p2in   <=  8'h00;
 
    end
 
  else
 
    begin
 
       p2in_s <=  p2_din & P2_EN_MSK;
 
       p2in   <=  p2in_s & P2_EN_MSK;
 
    end
 
 
 
 
// P2OUT Register
// P2OUT Register
//----------------
//----------------
reg  [7:0] p2out;
reg  [7:0] p2out;
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assign p2_sel = p2sel;
assign p2_sel = p2sel;
 
 
 
 
// P3IN Register
// P3IN Register
//---------------
//---------------
 
reg  [7:0] p3in_s;
reg  [7:0] p3in;
reg  [7:0] p3in;
 
 
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc)
  if (puc)      p3in <=  8'h00;
  if (puc)
  else          p3in <=  p3_din & P3_EN_MSK;
    begin
 
       p3in_s <=  8'h00;
 
       p3in   <=  8'h00;
 
    end
 
  else
 
    begin
 
       p3in_s <=  p3_din & P3_EN_MSK;
 
       p3in   <=  p3in_s & P3_EN_MSK;
 
    end
 
 
 
 
// P3OUT Register
// P3OUT Register
//----------------
//----------------
reg  [7:0] p3out;
reg  [7:0] p3out;
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assign p3_sel = p3sel;
assign p3_sel = p3sel;
 
 
 
 
// P4IN Register
// P4IN Register
//---------------
//---------------
 
reg  [7:0] p4in_s;
reg  [7:0] p4in;
reg  [7:0] p4in;
 
 
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc)
  if (puc)      p4in <=  8'h00;
  if (puc)
  else          p4in <=  p4_din & P4_EN_MSK;
    begin
 
       p4in_s <=  8'h00;
 
       p4in   <=  8'h00;
 
    end
 
  else
 
    begin
 
       p4in_s <=  p4_din & P4_EN_MSK;
 
       p4in   <=  p4in_s & P4_EN_MSK;
 
    end
 
 
 
 
// P4OUT Register
// P4OUT Register
//----------------
//----------------
reg  [7:0] p4out;
reg  [7:0] p4out;
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assign p4_sel = p4sel;
assign p4_sel = p4sel;
 
 
 
 
// P5IN Register
// P5IN Register
//---------------
//---------------
 
reg  [7:0] p5in_s;
reg  [7:0] p5in;
reg  [7:0] p5in;
 
 
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc)
  if (puc)      p5in <=  8'h00;
  if (puc)
  else          p5in <=  p5_din & P5_EN_MSK;
    begin
 
       p5in_s <=  8'h00;
 
       p5in   <=  8'h00;
 
    end
 
  else
 
    begin
 
       p5in_s <=  p5_din & P5_EN_MSK;
 
       p5in   <=  p5in_s & P5_EN_MSK;
 
    end
 
 
 
 
// P5OUT Register
// P5OUT Register
//----------------
//----------------
reg  [7:0] p5out;
reg  [7:0] p5out;
Line 592... Line 637...
assign p5_sel = p5sel;
assign p5_sel = p5sel;
 
 
 
 
// P6IN Register
// P6IN Register
//---------------
//---------------
 
reg  [7:0] p6in_s;
reg  [7:0] p6in;
reg  [7:0] p6in;
 
 
always @ (posedge mclk or posedge puc)
always @ (posedge mclk or posedge puc)
  if (puc)      p6in <=  8'h00;
  if (puc)
  else          p6in <=  p6_din & P6_EN_MSK;
    begin
 
       p6in_s <=  8'h00;
 
       p6in   <=  8'h00;
 
    end
 
  else
 
    begin
 
       p6in_s <=  p6_din & P6_EN_MSK;
 
       p6in   <=  p6in_s & P6_EN_MSK;
 
    end
 
 
 
 
// P6OUT Register
// P6OUT Register
//----------------
//----------------
reg  [7:0] p6out;
reg  [7:0] p6out;

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