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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_sfr.v] - Diff between revs 104 and 109

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Rev 104 Rev 109
Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 104 $
// $Rev: 109 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-06 21:02:27 +0100 (Sun, 06 Mar 2011) $
// $LastChangedDate: 2011-03-27 13:49:47 +0200 (Sun, 27 Mar 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
`endif
`endif
Line 53... Line 53...
    mclk,                         // Main system clock
    mclk,                         // Main system clock
    nmi_acc,                      // Non-Maskable interrupt request accepted
    nmi_acc,                      // Non-Maskable interrupt request accepted
    per_addr,                     // Peripheral address
    per_addr,                     // Peripheral address
    per_din,                      // Peripheral data input
    per_din,                      // Peripheral data input
    per_en,                       // Peripheral enable (high active)
    per_en,                       // Peripheral enable (high active)
    per_wen,                      // Peripheral write enable (high active)
    per_we,                       // Peripheral write enable (high active)
    por,                          // Power-on reset
    por,                          // Power-on reset
    puc,                          // Main system reset
    puc,                          // Main system reset
    wdtifg_clr,                   // Clear Watchdog-timer interrupt flag
    wdtifg_clr,                   // Clear Watchdog-timer interrupt flag
    wdtifg_set,                   // Set Watchdog-timer interrupt flag
    wdtifg_set,                   // Set Watchdog-timer interrupt flag
    wdtpw_error,                  // Watchdog-timer password error
    wdtpw_error,                  // Watchdog-timer password error
Line 77... Line 77...
input               mclk;         // Main system clock
input               mclk;         // Main system clock
input               nmi_acc;      // Non-Maskable interrupt request accepted
input               nmi_acc;      // Non-Maskable interrupt request accepted
input         [7:0] per_addr;     // Peripheral address
input         [7:0] per_addr;     // Peripheral address
input        [15:0] per_din;      // Peripheral data input
input        [15:0] per_din;      // Peripheral data input
input               per_en;       // Peripheral enable (high active)
input               per_en;       // Peripheral enable (high active)
input         [1:0] per_wen;      // Peripheral write enable (high active)
input         [1:0] per_we;       // Peripheral write enable (high active)
input               por;          // Power-on reset
input               por;          // Power-on reset
input               puc;          // Main system reset
input               puc;          // Main system reset
input               wdtifg_clr;   // Clear Watchdog-timer interrupt flag
input               wdtifg_clr;   // Clear Watchdog-timer interrupt flag
input               wdtifg_set;   // Set Watchdog-timer interrupt flag
input               wdtifg_set;   // Set Watchdog-timer interrupt flag
input               wdtpw_error;  // Watchdog-timer password error
input               wdtpw_error;  // Watchdog-timer password error
Line 113... Line 113...
    (IFG1 /2):     reg_dec  =  IFG1_D;
    (IFG1 /2):     reg_dec  =  IFG1_D;
    default  :     reg_dec  =  {256{1'b0}};
    default  :     reg_dec  =  {256{1'b0}};
  endcase
  endcase
 
 
// Read/Write probes
// Read/Write probes
wire         reg_lo_write =  per_wen[0] & per_en;
wire         reg_lo_write =  per_we[0] & per_en;
wire         reg_hi_write =  per_wen[1] & per_en;
wire         reg_hi_write =  per_we[1] & per_en;
wire         reg_read     = ~|per_wen   & per_en;
wire         reg_read     = ~|per_we   & per_en;
 
 
// Read/Write vectors
// Read/Write vectors
wire [255:0] reg_hi_wr    = reg_dec & {256{reg_hi_write}};
wire [255:0] reg_hi_wr    = reg_dec & {256{reg_hi_write}};
wire [255:0] reg_lo_wr    = reg_dec & {256{reg_lo_write}};
wire [255:0] reg_lo_wr    = reg_dec & {256{reg_lo_write}};
wire [255:0] reg_rd       = reg_dec & {256{reg_read}};
wire [255:0] reg_rd       = reg_dec & {256{reg_read}};

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