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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_clkmux.v] - Diff between revs 85 and 134

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Line 28... Line 28...
/*                                                                           */
/*                                                                           */
/* Author(s):                                                                */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* $Rev: 85 $                                                                */
/* $Rev: 134 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-01-28 22:05:37 +0100 (Fri, 28 Jan 2011) $          */
/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $          */
/*===========================================================================*/
/*===========================================================================*/
 
 
`define LONG_TIMEOUT
`define LONG_TIMEOUT
 
 
integer mclk_counter;
integer mclk_counter;
Line 51... Line 51...
      $display("|                 START SIMULATION              |");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
      $display(" ===============================================");
      repeat(5) @(posedge mclk);
      repeat(5) @(posedge mclk);
      stimulus_done = 0;
      stimulus_done = 0;
 
 
 
`ifdef WATCHDOG
 
 
      // WATCHDOG TEST INTERVAL MODE /64 - SMCLK == MCLK/2
      // WATCHDOG TEST INTERVAL MODE /64 - SMCLK == MCLK/2
      //--------------------------------------------------------
      //--------------------------------------------------------
 
 
      @(r15 === 16'h0001);
      @(r15 === 16'h0001);
      @(posedge r5[0]);
      @(posedge r5[0]);
      @(negedge mclk);
      @(negedge mclk);
      mclk_counter = 0;
      mclk_counter = 0;
      r5_counter   = 0;
      r5_counter   = 0;
      repeat(1024) @(negedge mclk);
      repeat(1024) @(negedge mclk);
      if (mclk_counter !== 1024) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK =====");
      if (mclk_counter !== 1024)        tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 1 =====");
      if (r5_counter   !== 8)    tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK =====");
   `ifdef ASIC
 
     `ifdef WATCHDOG_MUX
 
        `ifdef SMCLK_DIVIDER
 
            if (r5_counter   !== 7)     tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 2 =====");
 
        `else
 
            if (r5_counter   !== 14)    tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 3 =====");
 
        `endif
 
     `else
 
        `ifdef WATCHDOG_NOMUX_ACLK
 
           `ifdef LFXT_DOMAIN
 
               if (r5_counter   !== 0)  tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 4 =====");
 
           `else
 
               if (r5_counter   !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 5 =====");
 
           `endif
 
        `else
 
           `ifdef SMCLK_DIVIDER
 
               if (r5_counter   !== 7)  tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 6 =====");
 
           `else
 
               if (r5_counter   !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 7 =====");
 
           `endif
 
        `endif
 
     `endif
 
   `else
 
      if (r5_counter   !== 8)           tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 8 =====");
 
   `endif
 
 
 
 
      // WATCHDOG TEST INTERVAL MODE /64 - ACLK == LFXTCLK/1
      // WATCHDOG TEST INTERVAL MODE /64 - ACLK == LFXTCLK/1
      //--------------------------------------------------------
      //--------------------------------------------------------
 
 
Line 74... Line 99...
      @(negedge r5[0]);
      @(negedge r5[0]);
      @(negedge mclk);
      @(negedge mclk);
      mclk_counter = 0;
      mclk_counter = 0;
      r5_counter   = 0;
      r5_counter   = 0;
      repeat(7815) @(negedge mclk);
      repeat(7815) @(negedge mclk);
      if (mclk_counter !== 7815) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK =====");
      if (mclk_counter !== 7815)         tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 1 =====");
      if (r5_counter   !== 4)    tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK =====");
   `ifdef ASIC
 
     `ifdef WATCHDOG_MUX
 
            if (r5_counter      !== 4)   tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 2 =====");
 
     `else
 
        `ifdef WATCHDOG_NOMUX_ACLK
 
           `ifdef LFXT_DOMAIN
 
               if (r5_counter   !== 4)   tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 3 =====");
 
           `else
 
               if (r5_counter   !== 122) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 4 =====");
 
           `endif
 
        `else
 
             if (r5_counter     !== 122) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 5 =====");
 
        `endif
 
     `endif
 
   `else
 
      if (r5_counter   !== 4)            tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 6 =====");
 
   `endif
 
 
 
`else
 
      $display(" ===============================================");
 
      $display("|               SIMULATION SKIPPED              |");
 
      $display("|         (the Watchdog is not included)        |");
 
      $display(" ===============================================");
 
      $finish;
 
`endif
 
 
      stimulus_done = 1;
      stimulus_done = 1;
   end
   end
 
 
 
 
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