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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module.v] - Diff between revs 111 and 134

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Rev 111 Rev 134
Line 28... Line 28...
/*                                                                           */
/*                                                                           */
/* Author(s):                                                                */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* $Rev: 111 $                                                                */
/* $Rev: 134 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $          */
/*===========================================================================*/
/*===========================================================================*/
 
 
`define LONG_TIMEOUT
`define LONG_TIMEOUT
 
 
integer mclk_counter;
integer mclk_counter;
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      $display("|                 START SIMULATION              |");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
      $display(" ===============================================");
      repeat(5) @(posedge mclk);
      repeat(5) @(posedge mclk);
      stimulus_done = 0;
      stimulus_done = 0;
 
 
 
`ifdef ASIC
 
      $display(" ===============================================");
 
      $display("|               SIMULATION SKIPPED              |");
 
      $display("|   (this test is not supported in ASIC mode)   |");
 
      $display(" ===============================================");
 
      $finish;
 
`else
 
 
      // ACLK GENERATION
      // ACLK GENERATION
      //--------------------------------------------------------
      //--------------------------------------------------------
 
 
                                // ------- Divider /1 ----------
                                // ------- Divider /1 ----------
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      cpu_en        = 1'b0;
      cpu_en        = 1'b0;
      repeat(3)   @(posedge mclk);
      repeat(3)   @(posedge mclk);
      reg_val       = r14;           // Read R14 register & initialize aclk/smclk counters
      reg_val       = r14;           // Read R14 register & initialize aclk/smclk counters
      aclk_counter  = 0;
      aclk_counter  = 0;
      smclk_counter = 0;
      smclk_counter = 0;
 
      repeat(3)   @(posedge mclk);
      if (dbg_freeze    !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 2) =====");
      if (dbg_freeze    !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 2) =====");
 
 
      repeat(500) @(posedge mclk);   // Make sure that the CPU is stopped
      repeat(500) @(posedge mclk);   // Make sure that the CPU is stopped
      if (reg_val       !== r14)  tb_error("====== CPU is not stopped (test 3) =====");
      if (reg_val       !== r14)  tb_error("====== CPU is not stopped (test 3) =====");
      if (aclk_counter  !== 0)    tb_error("====== ACLK is not stopped (test 4) =====");
      if (aclk_counter  !== 0)    tb_error("====== ACLK is not stopped (test 4) =====");
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      if (r11 !== 16'h000e) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
      if (r11 !== 16'h000e) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
 
 
      if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
      if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
      if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
      if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
 
 
 
`endif
 
 
      stimulus_done = 1;
      stimulus_done = 1;
   end
   end
 
 
 
 
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