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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430_defines.v] - Diff between revs 106 and 111

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Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 106 $
// $Rev: 111 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//`define OMSP_NO_INCLUDE
//`define OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_undefines.v"
`include "openMSP430_undefines.v"
`endif
`endif
 
 
//----------------------------------------------------------------------------
//============================================================================
// SYSTEM CONFIGURATION
//============================================================================
//----------------------------------------------------------------------------
// BASIC SYSTEM CONFIGURATION
 
//============================================================================
 
//============================================================================
//
//
// Note: the sum of both program and data memories should not exceed 63.5 kB
// Note: the sum of program, data and peripheral memory spaces must not
 
//      exceed 64 kB
//
//
 
 
// Program Memory Size:
// Program Memory Size:
//                     Uncomment the required memory size
//                     Uncomment the required memory size
//-------------------------------------------------------
//-------------------------------------------------------
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//`define PMEM_SIZE_8_KB
//`define PMEM_SIZE_8_KB
//`define PMEM_SIZE_4_KB
//`define PMEM_SIZE_4_KB
`define PMEM_SIZE_2_KB
`define PMEM_SIZE_2_KB
//`define PMEM_SIZE_1_KB
//`define PMEM_SIZE_1_KB
 
 
 
 
// Data Memory Size:
// Data Memory Size:
//                     Uncomment the required memory size
//                     Uncomment the required memory size
//-------------------------------------------------------
//-------------------------------------------------------
//`define DMEM_SIZE_32_KB
//`define DMEM_SIZE_32_KB
//`define DMEM_SIZE_24_KB
//`define DMEM_SIZE_24_KB
Line 86... Line 90...
 
 
// Include/Exclude Hardware Multiplier
// Include/Exclude Hardware Multiplier
`define MULTIPLIER
`define MULTIPLIER
 
 
 
 
//----------------------------------------------------------------------------
// Include/Exclude Serial Debug interface
// REMOTE DEBUGGING INTERFACE CONFIGURATION
 
//----------------------------------------------------------------------------
 
 
 
// Include Debug interface
 
`define DBG_EN
`define DBG_EN
 
 
// Debug interface selection
 
//             `define DBG_UART -> Enable UART (8N1) debug interface
//============================================================================
//             `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
//============================================================================
 
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
 
//============================================================================
 
//============================================================================
 
 
 
//-------------------------------------------------------
 
// Peripheral Memory Space:
 
//-------------------------------------------------------
 
// The original MSP430 architecture map the peripherals
 
// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
 
// The following defines allow you to expand this space
 
// up to 32 kB (i.e. from 0x0000 to 0x7fff).
 
// As a consequence, the data memory mapping will be
 
// shifted up and a custom linker script will therefore
 
// be required by the GCC compiler.
 
//-------------------------------------------------------
 
//`define PER_SIZE_32_KB
 
//`define PER_SIZE_16_KB
 
//`define PER_SIZE_8_KB
 
//`define PER_SIZE_4_KB
 
//`define PER_SIZE_2_KB
 
//`define PER_SIZE_1_KB
 
`define PER_SIZE_512_B
 
 
 
 
 
//-------------------------------------------------------
 
// Defines the debugger CPU_CTL.RST_BRK_EN reset value
 
// (CPU break on PUC reset)
 
//-------------------------------------------------------
 
// When defined, the CPU will automatically break after
 
// a PUC occurrence by default. This is typically usefull
 
// when the program memory can only be initialized through
 
// the serial debug interface.
 
//-------------------------------------------------------
 
//`define DBG_RST_BRK_EN
 
 
 
 
 
//-------------------------------------------------------
 
// Custom user version number
 
//-------------------------------------------------------
 
// This 5 bit field can be freely used in order to allow
 
// custom identification of the system where the openMSP430
 
// is included through the debug interface.
 
// (see CPU_ID.USER_VERSION field in the documentation)
 
//-------------------------------------------------------
 
`define USER_VERSION 5'b00000
 
 
 
 
 
//============================================================================
 
//============================================================================
 
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
 
//============================================================================
 
//============================================================================
//
//
`define DBG_UART
// IMPORTANT NOTE:  Please update following configuration options ONLY if
//`define DBG_JTAG
//                 you have a good reason to do so... and if you know what
 
//                 you are doing :-P
 
//
 
//============================================================================
 
 
// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)
//-------------------------------------------------------
//             `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
// Number of hardware breakpoint units (each unit contains
//             `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
// two hardware address breakpoints):
//             `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
//             `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
//
//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
`define  DBG_HWBRK_0
//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
`define  DBG_HWBRK_1
//-------------------------------------------------------
`define  DBG_HWBRK_2
// Please keep in mind that hardware breakpoints only
`define  DBG_HWBRK_3
// make sense whenever the program memory is not an SRAM
 
// (i.e. Flash/OTP/ROM/...) or when you are interested
// Defines the debugger CPU_CTL.RST_BRK_EN reset value (CPU break on PUC reset)
// in data breakpoints (btw. not supported by GDB).
//
//-------------------------------------------------------
// When defined, this concretely bring the CPU to break after a PUC
//`define  DBG_HWBRK_0
// occurrence by default. This is typically usefull when the program
//`define  DBG_HWBRK_1
// memory can only be initialized through the serial debug interface.
//`define  DBG_HWBRK_2
 
//`define  DBG_HWBRK_3
 
 
 
 
 
//-------------------------------------------------------
 
// Enable/Disable the hardware breakpoint RANGE mode
 
//-------------------------------------------------------
 
// When enabled this feature allows the hardware breakpoint
 
// units to stop the cpu whenever an instruction or data
 
// access lays within an address range.
 
// Note that this feature is not supported by GDB.
 
//-------------------------------------------------------
 
//`define DBG_HWBRK_RANGE
 
 
 
 
 
//-------------------------------------------------------
 
// Input synchronizers
 
//-------------------------------------------------------
 
// In some cases, the asynchronous input ports might
 
// already be synchronized externally.
 
// If an extensive CDC design review showed that this
 
// is really the case,  the individual synchronizers
 
// can be disabled with the following defines.
 
//
 
// Notes:
 
//        - the dbg_en signal will reset the debug interface
 
//         when 0. Therefore make sure it is glitch free.
//
//
//`define DBG_RST_BRK_EN
//        - the dbg_uart_rxd synchronizer must be set to 1
 
//          when its reset is active.
 
//-------------------------------------------------------
 
`define SYNC_CPU_EN
 
`define SYNC_DBG_EN
 
`define SYNC_DBG_UART_RXD
 
`define SYNC_NMI
 
 
 
 
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
Line 131... Line 219...
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
 
 
//
//
// PROGRAM & DATA MEMORY CONFIGURATION
// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
//======================================
//==================================================
 
 
// Program Memory Size
// Program Memory Size
`ifdef PMEM_SIZE_59_KB
`ifdef PMEM_SIZE_59_KB
  `define PMEM_AWIDTH      15
  `define PMEM_AWIDTH      15
  `define PMEM_SIZE     60416
  `define PMEM_SIZE     60416
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`ifdef DMEM_SIZE_128_B
`ifdef DMEM_SIZE_128_B
  `define DMEM_AWIDTH        6
  `define DMEM_AWIDTH        6
  `define DMEM_SIZE        128
  `define DMEM_SIZE        128
`endif
`endif
 
 
 
// Peripheral Memory Size
 
`ifdef PER_SIZE_32_KB
 
  `define PER_AWIDTH        14
 
  `define PER_SIZE       32768
 
`endif
 
`ifdef PER_SIZE_16_KB
 
  `define PER_AWIDTH        13
 
  `define PER_SIZE       16384
 
`endif
 
`ifdef PER_SIZE_8_KB
 
  `define PER_AWIDTH        12
 
  `define PER_SIZE        8192
 
`endif
 
`ifdef PER_SIZE_4_KB
 
  `define PER_AWIDTH        11
 
  `define PER_SIZE        4096
 
`endif
 
`ifdef PER_SIZE_2_KB
 
  `define PER_AWIDTH        10
 
  `define PER_SIZE        2048
 
`endif
 
`ifdef PER_SIZE_1_KB
 
  `define PER_AWIDTH         9
 
  `define PER_SIZE        1024
 
`endif
 
`ifdef PER_SIZE_512_B
 
  `define PER_AWIDTH         8
 
  `define PER_SIZE         512
 
`endif
 
 
// Data Memory Base Adresses
// Data Memory Base Adresses
`define DMEM_BASE  16'h0200
`define DMEM_BASE  `PER_SIZE
 
 
// Program & Data Memory most significant address bit (for 16 bit words)
// Program & Data Memory most significant address bit (for 16 bit words)
`define PMEM_MSB   `PMEM_AWIDTH-1
`define PMEM_MSB   `PMEM_AWIDTH-1
`define DMEM_MSB   `DMEM_AWIDTH-1
`define DMEM_MSB   `DMEM_AWIDTH-1
 
`define PER_MSB    `PER_AWIDTH-1
 
 
//
//
// STATES, REGISTER FIELDS, ...
// STATES, REGISTER FIELDS, ...
//======================================
//======================================
 
 
Line 306... Line 425...
`define SYMB     4
`define SYMB     4
`define IMM      5
`define IMM      5
`define ABS      6
`define ABS      6
`define CONST    7
`define CONST    7
 
 
 
// Instruction state machine
 
`define I_IRQ_FETCH 3'h0
 
`define I_IRQ_DONE  3'h1
 
`define I_DEC       3'h2
 
`define I_EXT1      3'h3
 
`define I_EXT2      3'h4
 
`define I_IDLE      3'h5
 
 
// Execution state machine
// Execution state machine
`define E_IRQ_0    4'h0
`define E_IRQ_0    4'h0
`define E_IRQ_1    4'h1
`define E_IRQ_1    4'h1
`define E_IRQ_2    4'h2
`define E_IRQ_2    4'h2
`define E_IRQ_3    4'h3
`define E_IRQ_3    4'h3
Line 377... Line 504...
 
 
//
//
// DEBUG INTERFACE EXTRA CONFIGURATION
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
//======================================
 
 
 
// Debug interface: CPU version
 
`define CPU_VERSION   3'h1
 
 
// Debug interface: Software breakpoint opcode
// Debug interface: Software breakpoint opcode
`define DBG_SWBRK_OP 16'h4343
`define DBG_SWBRK_OP 16'h4343
 
 
// Debug UART interface auto data synchronization
// Debug UART interface auto data synchronization
// If the following define is commented out, then
// If the following define is commented out, then
Line 404... Line 534...
//`define DBG_UART_BAUD  921600
//`define DBG_UART_BAUD  921600
`define DBG_UART_BAUD 2000000
`define DBG_UART_BAUD 2000000
`define DBG_DCO_FREQ  20000000
`define DBG_DCO_FREQ  20000000
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
 
 
 
// Debug interface selection
 
//             `define DBG_UART -> Enable UART (8N1) debug interface
 
//             `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
 
//
 
`define DBG_UART
 
//`define DBG_JTAG
 
 
// Enable/Disable the hardware breakpoint RANGE mode
// Enable/Disable the hardware breakpoint RANGE mode
 
`ifdef DBG_HWBRK_RANGE
 
 `define HWBRK_RANGE 1'b1
 
`else
`define HWBRK_RANGE 1'b0
`define HWBRK_RANGE 1'b0
 
`endif
 
 
// Counter width for the debug interface UART
// Counter width for the debug interface UART
`define DBG_UART_XFER_CNT_W 16
`define DBG_UART_XFER_CNT_W 16
 
 
// Check configuration
// Check configuration

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