OpenCores

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [sim/] [tsu/] [gmii_rx_bfm.v] - Diff between revs 4 and 13

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 4 Rev 13
Line 14... Line 14...
end
end
assign #2 gmii_rxclk = gmii_rxclk_offset;
assign #2 gmii_rxclk = gmii_rxclk_offset;
 
 
integer feeder_file_rx, r_rx;
integer feeder_file_rx, r_rx;
integer start_addr_rx, end_addr_rx;
integer start_addr_rx, end_addr_rx;
integer index_rx;
integer index_rx, num_rx;
reg eof_rx;
reg eof_rx;
reg pcap_endian_rx;
reg pcap_endian_rx;
reg [31:0] pcap_4bytes_rx;
reg [31:0] pcap_4bytes_rx;
reg [31:0] packet_leng_rx;
reg [31:0] packet_leng_rx;
reg [ 7:0] packet_byte_rx;
reg [ 7:0] packet_byte_rx;
Line 41... Line 41...
        $fseek(feeder_file_rx, -4, 1);
        $fseek(feeder_file_rx, -4, 1);
        // skip pcap file header 24*8
        // skip pcap file header 24*8
        $fseek(feeder_file_rx, 24, 1);
        $fseek(feeder_file_rx, 24, 1);
        // read packet content
        // read packet content
        eof_rx = 0;
        eof_rx = 0;
 
        num_rx = 0;
        while (!eof_rx & !$feof(feeder_file_rx))
        while (!eof_rx & !$feof(feeder_file_rx))
        begin : fileread_loop
        begin : fileread_loop
            // skip frame header (8+4)*8
            // skip frame header (8+4)*8
            start_addr_rx = $ftell(feeder_file_rx);
            start_addr_rx = $ftell(feeder_file_rx);
            $fseek(feeder_file_rx, 8+4, 1);
            $fseek(feeder_file_rx, 8+4, 1);
Line 67... Line 68...
            begin
            begin
                @(posedge gmii_rxclk_offset)
                @(posedge gmii_rxclk_offset)
                gmii_rxctrl = 1'b0;
                gmii_rxctrl = 1'b0;
                gmii_rxdata = 8'h00;
                gmii_rxdata = 8'h00;
            end
            end
            // send frame pre-amble 555555d5=4*8
            // send frame preamble and sfd 5555555d=4*8
            repeat (3)
            repeat (3)
            begin
            begin
                @(posedge gmii_rxclk_offset);
                @(posedge gmii_rxclk_offset);
                gmii_rxctrl = 1'b1;
                gmii_rxctrl = 1'b1;
                gmii_rxdata = 8'h55;
                gmii_rxdata = 8'h55;
            end
            end
                @(posedge gmii_rxclk_offset)
                @(posedge gmii_rxclk_offset)
                gmii_rxctrl = 1'b1;
                gmii_rxctrl = 1'b1;
                gmii_rxdata = 8'hd5;
                gmii_rxdata = 8'h5d;
            // send frame content
            // send frame content
            for (index_rx=0; index_rx<packet_leng_rx; index_rx=index_rx+1)
            for (index_rx=0; index_rx<packet_leng_rx; index_rx=index_rx+1)
            begin
            begin
                r_rx = $fread(packet_byte_rx, feeder_file_rx);
                r_rx = $fread(packet_byte_rx, feeder_file_rx);
                @(posedge gmii_rxclk_offset);
                @(posedge gmii_rxclk_offset);
Line 95... Line 96...
                    gmii_rxdata = 8'h00;
                    gmii_rxdata = 8'h00;
                    disable fileread_loop;
                    disable fileread_loop;
                end
                end
            end
            end
            end_addr_rx = $ftell(feeder_file_rx);
            end_addr_rx = $ftell(feeder_file_rx);
 
            num_rx = num_rx + 1;
        end
        end
        $fclose(feeder_file_rx);
        $fclose(feeder_file_rx);
        gmii_rxctrl = 1'b0;
        gmii_rxctrl = 1'b0;
        gmii_rxdata = 8'h00;
        gmii_rxdata = 8'h00;
    end
    end
    #100 $stop;
 
end
end
 
 
 
 
endmodule
endmodule
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.