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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 204 and 210

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Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.2  2002/09/23 18:24:31  mohor
 
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
 
//
// Revision 1.1  2002/07/23 16:36:09  mohor
// Revision 1.1  2002/07/23 16:36:09  mohor
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
//
//
//
//
//
//
Line 51... Line 54...
`include "timescale.v"
`include "timescale.v"
 
 
module eth_spram_256x32(
module eth_spram_256x32(
        // Generic synchronous single-port RAM interface
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
        clk, rst, ce, we, oe, addr, di, do
 
 
 
`ifdef ETH_BIST
 
  ,trst, SO, SI, shift_DR, capture_DR, extest, tck
 
`endif
 
 
 
 
 
 
);
);
 
 
        //
        //
        // Generic synchronous single-port RAM interface
        // Generic synchronous single-port RAM interface
        //
        //
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        input  [7:0]    addr; // address bus inputs
        input  [7:0]    addr; // address bus inputs
        input  [31:0]   di;   // input data bus
        input  [31:0]   di;   // input data bus
        output [31:0]   do;   // output data bus
        output [31:0]   do;   // output data bus
 
 
 
 
 
`ifdef ETH_BIST
 
  input           trst;
 
  input           shift_DR, capture_DR, tck, extest;
 
  input           SI;
 
  output          SO;
 
`endif
 
 
`ifdef ETH_XILINX_RAMB4
`ifdef ETH_XILINX_RAMB4
 
 
    RAMB4_S16 ram0
    RAMB4_S16 ram0
    (
    (
        .DO      (do[15:0]),
        .DO      (do[15:0]),
Line 92... Line 109...
        .RST     (rst)
        .RST     (rst)
    );
    );
 
 
`else   // !ETH_XILINX_RAMB4
`else   // !ETH_XILINX_RAMB4
`ifdef  ETH_VIRTUAL_SILICON_RAM
`ifdef  ETH_VIRTUAL_SILICON_RAM
 
  `ifdef ETH_BIST
 
      vs_hdsp_256x32_bist ram0_bist
 
  `else
  vs_hdsp_256x32 ram0
  vs_hdsp_256x32 ram0
 
  `endif
  (
  (
        .CK       (clk),
        .CK       (clk),
        .CEN      (!ce),
        .CEN      (!ce),
        .WEN      (!we),
        .WEN      (!we),
        .OEN      (!oe),
        .OEN      (!oe),
        .ADR      (addr),
        .ADR      (addr),
        .DI       (di),
        .DI       (di),
        .DOUT     (do)
        .DOUT     (do)
 
 
 
      `ifdef ETH_BIST
 
        ,
 
        // reset
 
        .trst      (trst),
 
 
 
        // debug chain signals
 
        .SO        (SO),
 
        .SI        (SI),
 
        .shift_DR  (shift_DR),
 
        .capture_DR(capture_DR),
 
        .extest    (extest),
 
        .tck       (tck)
 
      `endif
  );
  );
 
 
`else   // !ETH_VIRTUAL_SILICON_RAM
`else   // !ETH_VIRTUAL_SILICON_RAM
 
 
        //
        //

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