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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Diff between revs 357 and 360

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Rev 357 Rev 360
Line 176... Line 176...
                      r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
                      r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
 
                      dbg_dat,
                      StartTxDone, TxClk, RxClk, SetPauseTimer
                      StartTxDone, TxClk, RxClk, SetPauseTimer
                    );
                    );
 
 
input [31:0] DataIn;
input [31:0] DataIn;
input [7:0] Address;
input [7:0] Address;
Line 266... Line 267...
input        StartTxDone;
input        StartTxDone;
input        TxClk;
input        TxClk;
input        RxClk;
input        RxClk;
input        SetPauseTimer;
input        SetPauseTimer;
 
 
 
input [31:0] dbg_dat; // debug data input
 
 
reg          irq_txb;
reg          irq_txb;
reg          irq_txe;
reg          irq_txe;
reg          irq_rxb;
reg          irq_rxb;
reg          irq_rxe;
reg          irq_rxe;
reg          irq_busy;
reg          irq_busy;
Line 309... Line 312...
wire MAC_ADDR1_Sel  = (Address == `ETH_MAC_ADDR1_ADR   );
wire MAC_ADDR1_Sel  = (Address == `ETH_MAC_ADDR1_ADR   );
wire HASH0_Sel      = (Address == `ETH_HASH0_ADR       );
wire HASH0_Sel      = (Address == `ETH_HASH0_ADR       );
wire HASH1_Sel      = (Address == `ETH_HASH1_ADR       );
wire HASH1_Sel      = (Address == `ETH_HASH1_ADR       );
wire TXCTRL_Sel     = (Address == `ETH_TX_CTRL_ADR     );
wire TXCTRL_Sel     = (Address == `ETH_TX_CTRL_ADR     );
wire RXCTRL_Sel     = (Address == `ETH_RX_CTRL_ADR     );
wire RXCTRL_Sel     = (Address == `ETH_RX_CTRL_ADR     );
 
wire DBG_REG_Sel    = (Address == `ETH_DBG_ADR         );
wire TX_BD_NUM_Sel  = (Address == `ETH_TX_BD_NUM_ADR   );
wire TX_BD_NUM_Sel  = (Address == `ETH_TX_BD_NUM_ADR   );
 
 
 
 
wire [2:0] MODER_Wr;
wire [2:0] MODER_Wr;
wire [0:0] INT_SOURCE_Wr;
wire [0:0] INT_SOURCE_Wr;
Line 400... Line 404...
wire [31:0] MAC_ADDR1Out;
wire [31:0] MAC_ADDR1Out;
wire [31:0] TX_BD_NUMOut;
wire [31:0] TX_BD_NUMOut;
wire [31:0] HASH0Out;
wire [31:0] HASH0Out;
wire [31:0] HASH1Out;
wire [31:0] HASH1Out;
wire [31:0] TXCTRLOut;
wire [31:0] TXCTRLOut;
 
wire [31:0] DBGOut;
 
 
// MODER Register
// MODER Register
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0)        MODER_0
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0)        MODER_0
  (
  (
   .DataIn    (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
   .DataIn    (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
Line 869... Line 874...
        `ETH_MAC_ADDR1_ADR    :  DataOut=MAC_ADDR1Out;
        `ETH_MAC_ADDR1_ADR    :  DataOut=MAC_ADDR1Out;
        `ETH_TX_BD_NUM_ADR    :  DataOut=TX_BD_NUMOut;
        `ETH_TX_BD_NUM_ADR    :  DataOut=TX_BD_NUMOut;
        `ETH_HASH0_ADR        :  DataOut=HASH0Out;
        `ETH_HASH0_ADR        :  DataOut=HASH0Out;
        `ETH_HASH1_ADR        :  DataOut=HASH1Out;
        `ETH_HASH1_ADR        :  DataOut=HASH1Out;
        `ETH_TX_CTRL_ADR      :  DataOut=TXCTRLOut;
        `ETH_TX_CTRL_ADR      :  DataOut=TXCTRLOut;
 
        `ETH_DBG_ADR          :  DataOut=dbg_dat;
        default:             DataOut=32'h0;
        default:             DataOut=32'h0;
      endcase
      endcase
    end
    end
  else
  else
    DataOut=32'h0;
    DataOut=32'h0;

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