OpenCores

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_receivecontrol.v] - Diff between revs 346 and 352

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 346 Rev 352
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  eth_receivecontrol.v                                        ////
////  eth_receivecontrol.v                                        ////
////                                                              ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/project,ethmac                     ////
////  http://www.opencores.org/project,ethmac                     ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/11/22 01:57:06  mohor
// Revision 1.4  2002/11/22 01:57:06  mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
// synchronized.
//
//
// Revision 1.3  2002/01/23 10:28:16  mohor
// Revision 1.3  2002/01/23 10:28:16  mohor
// Link in the header changed.
// Link in the header changed.
//
//
// Revision 1.2  2001/10/19 08:43:51  mohor
// Revision 1.2  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
// simulation of the few cores in a one joined project.
//
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
// is done due to the ASIC tools.
//
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
// Directory structure changed. Files checked and joind together.
//
//
// Revision 1.1  2001/07/03 12:51:54  mohor
// Revision 1.1  2001/07/03 12:51:54  mohor
// Initial release of the MAC Control module.
// Initial release of the MAC Control module.
//
//
//
//
//
//
//
//
//
//
 
 
 
 
`include "timescale.v"
`include "timescale.v"
 
 
 
 
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
                           RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
                           RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
                           TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
                           TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
                           TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
                           TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
                           RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
                           RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
                          );
                          );
 
 
parameter Tp = 1;
 
 
 
 
 
input       MTxClk;
input       MTxClk;
input       MRxClk;
input       MRxClk;
input       TxReset;
input       TxReset;
input       RxReset;
input       RxReset;
input [7:0] RxData;
input [7:0] RxData;
input       RxValid;
input       RxValid;
input       RxStartFrm;
input       RxStartFrm;
input       RxEndFrm;
input       RxEndFrm;
input       RxFlow;
input       RxFlow;
input       ReceiveEnd;
input       ReceiveEnd;
input [47:0]MAC;
input [47:0]MAC;
input       DlyCrcEn;
input       DlyCrcEn;
input       TxDoneIn;
input       TxDoneIn;
input       TxAbortIn;
input       TxAbortIn;
input       TxStartFrmOut;
input       TxStartFrmOut;
input       ReceivedLengthOK;
input       ReceivedLengthOK;
input       ReceivedPacketGood;
input       ReceivedPacketGood;
input       TxUsedDataOutDetected;
input       TxUsedDataOutDetected;
input       RxStatusWriteLatched_sync2;
input       RxStatusWriteLatched_sync2;
input       r_PassAll;
input       r_PassAll;
 
 
output      Pause;
output      Pause;
output      ReceivedPauseFrm;
output      ReceivedPauseFrm;
output      AddressOK;
output      AddressOK;
output      SetPauseTimer;
output      SetPauseTimer;
 
 
 
 
reg         Pause;
reg         Pause;
reg         AddressOK;                // Multicast or unicast address detected
reg         AddressOK;                // Multicast or unicast address detected
reg         TypeLengthOK;             // Type/Length field contains 0x8808
reg         TypeLengthOK;             // Type/Length field contains 0x8808
reg         DetectionWindow;          // Detection of the PAUSE frame is possible within this window
reg         DetectionWindow;          // Detection of the PAUSE frame is possible within this window
reg         OpCodeOK;                 // PAUSE opcode detected (0x0001)
reg         OpCodeOK;                 // PAUSE opcode detected (0x0001)
reg  [2:0]  DlyCrcCnt;
reg  [2:0]  DlyCrcCnt;
reg  [4:0]  ByteCnt;
reg  [4:0]  ByteCnt;
reg [15:0]  AssembledTimerValue;
reg [15:0]  AssembledTimerValue;
reg [15:0]  LatchedTimerValue;
reg [15:0]  LatchedTimerValue;
reg         ReceivedPauseFrm;
reg         ReceivedPauseFrm;
reg         ReceivedPauseFrmWAddr;
reg         ReceivedPauseFrmWAddr;
reg         PauseTimerEq0_sync1;
reg         PauseTimerEq0_sync1;
reg         PauseTimerEq0_sync2;
reg         PauseTimerEq0_sync2;
reg [15:0]  PauseTimer;
reg [15:0]  PauseTimer;
reg         Divider2;
reg         Divider2;
reg  [5:0]  SlotTimer;
reg  [5:0]  SlotTimer;
 
 
wire [47:0] ReservedMulticast;        // 0x0180C2000001
wire [47:0] ReservedMulticast;        // 0x0180C2000001
wire [15:0] TypeLength;               // 0x8808
wire [15:0] TypeLength;               // 0x8808
wire        ResetByteCnt;             // 
wire        ResetByteCnt;             // 
wire        IncrementByteCnt;         // 
wire        IncrementByteCnt;         // 
wire        ByteCntEq0;               // ByteCnt = 0
wire        ByteCntEq0;               // ByteCnt = 0
wire        ByteCntEq1;               // ByteCnt = 1
wire        ByteCntEq1;               // ByteCnt = 1
wire        ByteCntEq2;               // ByteCnt = 2
wire        ByteCntEq2;               // ByteCnt = 2
wire        ByteCntEq3;               // ByteCnt = 3
wire        ByteCntEq3;               // ByteCnt = 3
wire        ByteCntEq4;               // ByteCnt = 4
wire        ByteCntEq4;               // ByteCnt = 4
wire        ByteCntEq5;               // ByteCnt = 5
wire        ByteCntEq5;               // ByteCnt = 5
wire        ByteCntEq12;              // ByteCnt = 12
wire        ByteCntEq12;              // ByteCnt = 12
wire        ByteCntEq13;              // ByteCnt = 13
wire        ByteCntEq13;              // ByteCnt = 13
wire        ByteCntEq14;              // ByteCnt = 14
wire        ByteCntEq14;              // ByteCnt = 14
wire        ByteCntEq15;              // ByteCnt = 15
wire        ByteCntEq15;              // ByteCnt = 15
wire        ByteCntEq16;              // ByteCnt = 16
wire        ByteCntEq16;              // ByteCnt = 16
wire        ByteCntEq17;              // ByteCnt = 17
wire        ByteCntEq17;              // ByteCnt = 17
wire        ByteCntEq18;              // ByteCnt = 18
wire        ByteCntEq18;              // ByteCnt = 18
wire        DecrementPauseTimer;      // 
wire        DecrementPauseTimer;      // 
wire        PauseTimerEq0;            // 
wire        PauseTimerEq0;            // 
wire        ResetSlotTimer;           // 
wire        ResetSlotTimer;           // 
wire        IncrementSlotTimer;       // 
wire        IncrementSlotTimer;       // 
wire        SlotFinished;             // 
wire        SlotFinished;             // 
 
 
 
 
 
 
// Reserved multicast address and Type/Length for PAUSE control
// Reserved multicast address and Type/Length for PAUSE control
assign ReservedMulticast = 48'h0180C2000001;
assign ReservedMulticast = 48'h0180C2000001;
assign TypeLength = 16'h8808;
assign TypeLength = 16'h8808;
 
 
 
 
// Address Detection (Multicast or unicast)
// Address Detection (Multicast or unicast)
always @ (posedge MRxClk or posedge RxReset)
always @ (posedge MRxClk or posedge RxReset)
begin
begin
  if(RxReset)
  if(RxReset)
    AddressOK <= #Tp 1'b0;
    AddressOK <=  1'b0;
  else
  else
  if(DetectionWindow & ByteCntEq0)
  if(DetectionWindow & ByteCntEq0)
    AddressOK <= #Tp  RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
    AddressOK <=   RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
  else
  else
  if(DetectionWindow & ByteCntEq1)
  if(DetectionWindow & ByteCntEq1)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
    AddressOK <=  (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
  else
  else
  if(DetectionWindow & ByteCntEq2)
  if(DetectionWindow & ByteCntEq2)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
    AddressOK <=  (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
  else
  else
  if(DetectionWindow & ByteCntEq3)
  if(DetectionWindow & ByteCntEq3)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
    AddressOK <=  (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
  else
  else
  if(DetectionWindow & ByteCntEq4)
  if(DetectionWindow & ByteCntEq4)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8]  | RxData[7:0] == MAC[15:8])  & AddressOK;
    AddressOK <=  (RxData[7:0] == ReservedMulticast[15:8]  | RxData[7:0] == MAC[15:8])  & AddressOK;
  else
  else
  if(DetectionWindow & ByteCntEq5)
  if(DetectionWindow & ByteCntEq5)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0]   | RxData[7:0] == MAC[7:0])   & AddressOK;
    AddressOK <=  (RxData[7:0] == ReservedMulticast[7:0]   | RxData[7:0] == MAC[7:0])   & AddressOK;
  else
  else
  if(ReceiveEnd)
  if(ReceiveEnd)
    AddressOK <= #Tp 1'b0;
    AddressOK <=  1'b0;
end
end
 
 
 
 
 
 
// TypeLengthOK (Type/Length Control frame detected)
// TypeLengthOK (Type/Length Control frame detected)
always @ (posedge MRxClk or posedge RxReset )
always @ (posedge MRxClk or posedge RxReset )
begin
begin
  if(RxReset)
  if(RxReset)
    TypeLengthOK <= #Tp 1'b0;
    TypeLengthOK <=  1'b0;
  else
  else
  if(DetectionWindow & ByteCntEq12)
  if(DetectionWindow & ByteCntEq12)
    TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
    TypeLengthOK <=  ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
  else
  else
  if(DetectionWindow & ByteCntEq13)
  if(DetectionWindow & ByteCntEq13)
    TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
    TypeLengthOK <=  ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
  else
  else
  if(ReceiveEnd)
  if(ReceiveEnd)
    TypeLengthOK <= #Tp 1'b0;
    TypeLengthOK <=  1'b0;
end
end
 
 
 
 
 
 
// Latch Control Frame Opcode
// Latch Control Frame Opcode
always @ (posedge MRxClk or posedge RxReset )
always @ (posedge MRxClk or posedge RxReset )
begin
begin
  if(RxReset)
  if(RxReset)
    OpCodeOK <= #Tp 1'b0;
    OpCodeOK <=  1'b0;
  else
  else
  if(ByteCntEq16)
  if(ByteCntEq16)
    OpCodeOK <= #Tp 1'b0;
    OpCodeOK <=  1'b0;
  else
  else
    begin
    begin
      if(DetectionWindow & ByteCntEq14)
      if(DetectionWindow & ByteCntEq14)
        OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00;
        OpCodeOK <=  ByteCntEq14 & RxData[7:0] == 8'h00;
 
 
      if(DetectionWindow & ByteCntEq15)
      if(DetectionWindow & ByteCntEq15)
        OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
        OpCodeOK <=  ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
    end
    end
end
end
 
 
 
 
// ReceivedPauseFrmWAddr (+Address Check)
// ReceivedPauseFrmWAddr (+Address Check)
always @ (posedge MRxClk or posedge RxReset )
always @ (posedge MRxClk or posedge RxReset )
begin
begin
  if(RxReset)
  if(RxReset)
    ReceivedPauseFrmWAddr <= #Tp 1'b0;
    ReceivedPauseFrmWAddr <=  1'b0;
  else
  else
  if(ReceiveEnd)
  if(ReceiveEnd)
    ReceivedPauseFrmWAddr <= #Tp 1'b0;
    ReceivedPauseFrmWAddr <=  1'b0;
  else
  else
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
    ReceivedPauseFrmWAddr <= #Tp 1'b1;
    ReceivedPauseFrmWAddr <=  1'b1;
end
end
 
 
 
 
 
 
// Assembling 16-bit timer value from two 8-bit data
// Assembling 16-bit timer value from two 8-bit data
always @ (posedge MRxClk or posedge RxReset )
always @ (posedge MRxClk or posedge RxReset )
begin
begin
  if(RxReset)
  if(RxReset)
    AssembledTimerValue[15:0] <= #Tp 16'h0;
    AssembledTimerValue[15:0] <=  16'h0;
  else
  else
  if(RxStartFrm)
  if(RxStartFrm)
    AssembledTimerValue[15:0] <= #Tp 16'h0;
    AssembledTimerValue[15:0] <=  16'h0;
  else
  else
    begin
    begin
      if(DetectionWindow & ByteCntEq16)
      if(DetectionWindow & ByteCntEq16)
        AssembledTimerValue[15:8] <= #Tp RxData[7:0];
        AssembledTimerValue[15:8] <=  RxData[7:0];
      if(DetectionWindow & ByteCntEq17)
      if(DetectionWindow & ByteCntEq17)
        AssembledTimerValue[7:0] <= #Tp RxData[7:0];
        AssembledTimerValue[7:0] <=  RxData[7:0];
    end
    end
end
end
 
 
 
 
// Detection window (while PAUSE detection is possible)
// Detection window (while PAUSE detection is possible)
always @ (posedge MRxClk or posedge RxReset )
always @ (posedge MRxClk or posedge RxReset )
begin
begin
  if(RxReset)
  if(RxReset)
    DetectionWindow <= #Tp 1'b1;
    DetectionWindow <=  1'b1;
  else
  else
  if(ByteCntEq18)
  if(ByteCntEq18)
    DetectionWindow <= #Tp 1'b0;
    DetectionWindow <=  1'b0;
  else
  else
  if(ReceiveEnd)
  if(ReceiveEnd)
    DetectionWindow <= #Tp 1'b1;
    DetectionWindow <=  1'b1;
end
end
 
 
 
 
 
 
// Latching Timer Value
// Latching Timer Value
always @ (posedge MRxClk or posedge RxReset )
always @ (posedge MRxClk or posedge RxReset )
begin
begin
  if(RxReset)
  if(RxReset)
    LatchedTimerValue[15:0] <= #Tp 16'h0;
    LatchedTimerValue[15:0] <=  16'h0;
  else
  else
  if(DetectionWindow &  ReceivedPauseFrmWAddr &  ByteCntEq18)
  if(DetectionWindow &  ReceivedPauseFrmWAddr &  ByteCntEq18)
    LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];
    LatchedTimerValue[15:0] <=  AssembledTimerValue[15:0];
  else
  else
  if(ReceiveEnd)
  if(ReceiveEnd)
    LatchedTimerValue[15:0] <= #Tp 16'h0;
    LatchedTimerValue[15:0] <=  16'h0;
end
end
 
 
 
 
 
 
// Delayed CEC counter
// Delayed CEC counter
always @ (posedge MRxClk or posedge RxReset)
always @ (posedge MRxClk or posedge RxReset)
begin
begin
  if(RxReset)
  if(RxReset)
    DlyCrcCnt <= #Tp 3'h0;
    DlyCrcCnt <=  3'h0;
  else
  else
  if(RxValid & RxEndFrm)
  if(RxValid & RxEndFrm)
    DlyCrcCnt <= #Tp 3'h0;
    DlyCrcCnt <=  3'h0;
  else
  else
  if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
  if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
    DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
    DlyCrcCnt <=  DlyCrcCnt + 1'b1;
end
end
 
 
 
 
assign ResetByteCnt = RxEndFrm;
assign ResetByteCnt = RxEndFrm;
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
 
 
 
 
// Byte counter
// Byte counter
always @ (posedge MRxClk or posedge RxReset)
always @ (posedge MRxClk or posedge RxReset)
begin
begin
  if(RxReset)
  if(RxReset)
    ByteCnt[4:0] <= #Tp 5'h0;
    ByteCnt[4:0] <=  5'h0;
  else
  else
  if(ResetByteCnt)
  if(ResetByteCnt)
    ByteCnt[4:0] <= #Tp 5'h0;
    ByteCnt[4:0] <=  5'h0;
  else
  else
  if(IncrementByteCnt)
  if(IncrementByteCnt)
    ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1;
    ByteCnt[4:0] <=  ByteCnt[4:0] + 1'b1;
end
end
 
 
 
 
assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
 
 
 
 
assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
assign DecrementPauseTimer = SlotFinished & |PauseTimer;
assign DecrementPauseTimer = SlotFinished & |PauseTimer;
 
 
 
 
// PauseTimer[15:0]
// PauseTimer[15:0]
always @ (posedge MRxClk or posedge RxReset)
always @ (posedge MRxClk or posedge RxReset)
begin
begin
  if(RxReset)
  if(RxReset)
    PauseTimer[15:0] <= #Tp 16'h0;
    PauseTimer[15:0] <=  16'h0;
  else
  else
  if(SetPauseTimer)
  if(SetPauseTimer)
    PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0];
    PauseTimer[15:0] <=  LatchedTimerValue[15:0];
  else
  else
  if(DecrementPauseTimer)
  if(DecrementPauseTimer)
    PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1;
    PauseTimer[15:0] <=  PauseTimer[15:0] - 1'b1;
end
end
 
 
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
 
 
 
 
 
 
// Synchronization of the pause timer
// Synchronization of the pause timer
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    begin
    begin
      PauseTimerEq0_sync1 <= #Tp 1'b1;
      PauseTimerEq0_sync1 <=  1'b1;
      PauseTimerEq0_sync2 <= #Tp 1'b1;
      PauseTimerEq0_sync2 <=  1'b1;
    end
    end
  else
  else
    begin
    begin
      PauseTimerEq0_sync1 <= #Tp PauseTimerEq0;
      PauseTimerEq0_sync1 <=  PauseTimerEq0;
      PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1;
      PauseTimerEq0_sync2 <=  PauseTimerEq0_sync1;
    end
    end
end
end
 
 
 
 
// Pause signal generation
// Pause signal generation
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    Pause <= #Tp 1'b0;
    Pause <=  1'b0;
  else
  else
  if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
  if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
    Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2;
    Pause <=  RxFlow & ~PauseTimerEq0_sync2;
end
end
 
 
 
 
// Divider2 is used for incrementing the Slot timer every other clock
// Divider2 is used for incrementing the Slot timer every other clock
always @ (posedge MRxClk or posedge RxReset)
always @ (posedge MRxClk or posedge RxReset)
begin
begin
  if(RxReset)
  if(RxReset)
    Divider2 <= #Tp 1'b0;
    Divider2 <=  1'b0;
  else
  else
  if(|PauseTimer[15:0] & RxFlow)
  if(|PauseTimer[15:0] & RxFlow)
    Divider2 <= #Tp ~Divider2;
    Divider2 <=  ~Divider2;
  else
  else
    Divider2 <= #Tp 1'b0;
    Divider2 <=  1'b0;
end
end
 
 
 
 
assign ResetSlotTimer = RxReset;
assign ResetSlotTimer = RxReset;
assign IncrementSlotTimer =  Pause & RxFlow & Divider2;
assign IncrementSlotTimer =  Pause & RxFlow & Divider2;
 
 
 
 
// SlotTimer
// SlotTimer
always @ (posedge MRxClk or posedge RxReset)
always @ (posedge MRxClk or posedge RxReset)
begin
begin
  if(RxReset)
  if(RxReset)
    SlotTimer[5:0] <= #Tp 6'h0;
    SlotTimer[5:0] <=  6'h0;
  else
  else
  if(ResetSlotTimer)
  if(ResetSlotTimer)
    SlotTimer[5:0] <= #Tp 6'h0;
    SlotTimer[5:0] <=  6'h0;
  else
  else
  if(IncrementSlotTimer)
  if(IncrementSlotTimer)
    SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1;
    SlotTimer[5:0] <=  SlotTimer[5:0] + 1'b1;
end
end
 
 
 
 
assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer;  // Slot is 512 bits (64 bytes)
assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer;  // Slot is 512 bits (64 bytes)
 
 
 
 
 
 
// Pause Frame received
// Pause Frame received
always @ (posedge MRxClk or posedge RxReset)
always @ (posedge MRxClk or posedge RxReset)
begin
begin
  if(RxReset)
  if(RxReset)
    ReceivedPauseFrm <=#Tp 1'b0;
    ReceivedPauseFrm <= 1'b0;
  else
  else
  if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
  if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
    ReceivedPauseFrm <=#Tp 1'b0;
    ReceivedPauseFrm <= 1'b0;
  else
  else
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
    ReceivedPauseFrm <=#Tp 1'b1;
    ReceivedPauseFrm <= 1'b1;
end
end
 
 
 
 
endmodule
endmodule
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.