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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_random.v] - Diff between revs 346 and 352

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Rev 346 Rev 352
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`include "timescale.v"
`include "timescale.v"
 
 
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
                   RandomEq0, RandomEqByteCnt);
                   RandomEq0, RandomEqByteCnt);
 
 
parameter Tp = 1;
 
 
 
input MTxClk;
input MTxClk;
input Reset;
input Reset;
input StateJam;
input StateJam;
input StateJam_q;
input StateJam_q;
input [3:0] RetryCnt;
input [3:0] RetryCnt;
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always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    x[9:0] <= #Tp 0;
    x[9:0] <=  0;
  else
  else
    x[9:0] <= #Tp {x[8:0], Feedback};
    x[9:0] <=  {x[8:0], Feedback};
end
end
 
 
assign Feedback = ~(x[2] ^ x[9]);
assign Feedback = ~(x[2] ^ x[9]);
 
 
assign Random [0] = x[0];
assign Random [0] = x[0];
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always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RandomLatched <= #Tp 10'h000;
    RandomLatched <=  10'h000;
  else
  else
    begin
    begin
      if(StateJam & StateJam_q)
      if(StateJam & StateJam_q)
        RandomLatched <= #Tp Random;
        RandomLatched <=  Random;
    end
    end
end
end
 
 
// Random Number == 0      IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
// Random Number == 0      IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
assign RandomEq0 = RandomLatched == 10'h0;
assign RandomEq0 = RandomLatched == 10'h0;

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