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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_miim.v] - Diff between revs 349 and 352

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Rev 349 Rev 352
Line 133... Line 133...
 
 
output        WCtrlDataStart;     // This signals resets the WCTRLDATA bit in the MIIM Command register
output        WCtrlDataStart;     // This signals resets the WCTRLDATA bit in the MIIM Command register
output        RStatStart;         // This signal resets the RSTAT BIT in the MIIM Command register
output        RStatStart;         // This signal resets the RSTAT BIT in the MIIM Command register
output        UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
output        UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
 
 
parameter Tp = 1;
 
 
 
 
 
reg           Nvalid;
reg           Nvalid;
reg           EndBusy_d;          // Pre-end Busy signal
reg           EndBusy_d;          // Pre-end Busy signal
reg           EndBusy;            // End Busy signal (stops the operation in progress)
reg           EndBusy;            // End Busy signal (stops the operation in progress)
 
 
Line 196... Line 194...
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      EndBusy_d <= #Tp 1'b0;
      EndBusy_d <=  1'b0;
      EndBusy <= #Tp 1'b0;
      EndBusy <=  1'b0;
    end
    end
  else
  else
    begin
    begin
      EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;
      EndBusy_d <=  ~InProgress_q2 & InProgress_q3;
      EndBusy   <= #Tp EndBusy_d;
      EndBusy   <=  EndBusy_d;
    end
    end
end
end
 
 
 
 
// Update MII RX_DATA register
// Update MII RX_DATA register
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    UpdateMIIRX_DATAReg <= #Tp 0;
    UpdateMIIRX_DATAReg <=  0;
  else
  else
  if(EndBusy & ~WCtrlDataStart_q)
  if(EndBusy & ~WCtrlDataStart_q)
    UpdateMIIRX_DATAReg <= #Tp 1;
    UpdateMIIRX_DATAReg <=  1;
  else
  else
    UpdateMIIRX_DATAReg <= #Tp 0;
    UpdateMIIRX_DATAReg <=  0;
end
end
 
 
 
 
 
 
// Generation of the delayed signals used for positive edge triggering.
// Generation of the delayed signals used for positive edge triggering.
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      WCtrlData_q1 <= #Tp 1'b0;
      WCtrlData_q1 <=  1'b0;
      WCtrlData_q2 <= #Tp 1'b0;
      WCtrlData_q2 <=  1'b0;
      WCtrlData_q3 <= #Tp 1'b0;
      WCtrlData_q3 <=  1'b0;
 
 
      RStat_q1 <= #Tp 1'b0;
      RStat_q1 <=  1'b0;
      RStat_q2 <= #Tp 1'b0;
      RStat_q2 <=  1'b0;
      RStat_q3 <= #Tp 1'b0;
      RStat_q3 <=  1'b0;
 
 
      ScanStat_q1  <= #Tp 1'b0;
      ScanStat_q1  <=  1'b0;
      ScanStat_q2  <= #Tp 1'b0;
      ScanStat_q2  <=  1'b0;
      SyncStatMdcEn <= #Tp 1'b0;
      SyncStatMdcEn <=  1'b0;
    end
    end
  else
  else
    begin
    begin
      WCtrlData_q1 <= #Tp WCtrlData;
      WCtrlData_q1 <=  WCtrlData;
      WCtrlData_q2 <= #Tp WCtrlData_q1;
      WCtrlData_q2 <=  WCtrlData_q1;
      WCtrlData_q3 <= #Tp WCtrlData_q2;
      WCtrlData_q3 <=  WCtrlData_q2;
 
 
      RStat_q1 <= #Tp RStat;
      RStat_q1 <=  RStat;
      RStat_q2 <= #Tp RStat_q1;
      RStat_q2 <=  RStat_q1;
      RStat_q3 <= #Tp RStat_q2;
      RStat_q3 <=  RStat_q2;
 
 
      ScanStat_q1  <= #Tp ScanStat;
      ScanStat_q1  <=  ScanStat;
      ScanStat_q2  <= #Tp ScanStat_q1;
      ScanStat_q2  <=  ScanStat_q1;
      if(MdcEn)
      if(MdcEn)
        SyncStatMdcEn  <= #Tp ScanStat_q2;
        SyncStatMdcEn  <=  ScanStat_q2;
    end
    end
end
end
 
 
 
 
// Generation of the Start Commands (Write Control Data or Read Status)
// Generation of the Start Commands (Write Control Data or Read Status)
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      WCtrlDataStart <= #Tp 1'b0;
      WCtrlDataStart <=  1'b0;
      WCtrlDataStart_q <= #Tp 1'b0;
      WCtrlDataStart_q <=  1'b0;
      RStatStart <= #Tp 1'b0;
      RStatStart <=  1'b0;
    end
    end
  else
  else
    begin
    begin
      if(EndBusy)
      if(EndBusy)
        begin
        begin
          WCtrlDataStart <= #Tp 1'b0;
          WCtrlDataStart <=  1'b0;
          RStatStart <= #Tp 1'b0;
          RStatStart <=  1'b0;
        end
        end
      else
      else
        begin
        begin
          if(WCtrlData_q2 & ~WCtrlData_q3)
          if(WCtrlData_q2 & ~WCtrlData_q3)
            WCtrlDataStart <= #Tp 1'b1;
            WCtrlDataStart <=  1'b1;
          if(RStat_q2 & ~RStat_q3)
          if(RStat_q2 & ~RStat_q3)
            RStatStart <= #Tp 1'b1;
            RStatStart <=  1'b1;
          WCtrlDataStart_q <= #Tp WCtrlDataStart;
          WCtrlDataStart_q <=  WCtrlDataStart;
        end
        end
    end
    end
end
end
 
 
 
 
// Generation of the Nvalid signal (indicates when the status is invalid)
// Generation of the Nvalid signal (indicates when the status is invalid)
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    Nvalid <= #Tp 1'b0;
    Nvalid <=  1'b0;
  else
  else
    begin
    begin
      if(~InProgress_q2 & InProgress_q3)
      if(~InProgress_q2 & InProgress_q3)
        begin
        begin
          Nvalid <= #Tp 1'b0;
          Nvalid <=  1'b0;
        end
        end
      else
      else
        begin
        begin
          if(ScanStat_q2  & ~SyncStatMdcEn)
          if(ScanStat_q2  & ~SyncStatMdcEn)
            Nvalid <= #Tp 1'b1;
            Nvalid <=  1'b1;
        end
        end
    end
    end
end
end
 
 
// Signals used for the generation of the Operation signals (positive edge)
// Signals used for the generation of the Operation signals (positive edge)
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      WCtrlDataStart_q1 <= #Tp 1'b0;
      WCtrlDataStart_q1 <=  1'b0;
      WCtrlDataStart_q2 <= #Tp 1'b0;
      WCtrlDataStart_q2 <=  1'b0;
 
 
      RStatStart_q1 <= #Tp 1'b0;
      RStatStart_q1 <=  1'b0;
      RStatStart_q2 <= #Tp 1'b0;
      RStatStart_q2 <=  1'b0;
 
 
      InProgress_q1 <= #Tp 1'b0;
      InProgress_q1 <=  1'b0;
      InProgress_q2 <= #Tp 1'b0;
      InProgress_q2 <=  1'b0;
      InProgress_q3 <= #Tp 1'b0;
      InProgress_q3 <=  1'b0;
 
 
          LatchByte0_d <= #Tp 1'b0;
          LatchByte0_d <=  1'b0;
          LatchByte1_d <= #Tp 1'b0;
          LatchByte1_d <=  1'b0;
 
 
          LatchByte <= #Tp 2'b00;
          LatchByte <=  2'b00;
    end
    end
  else
  else
    begin
    begin
      if(MdcEn)
      if(MdcEn)
        begin
        begin
          WCtrlDataStart_q1 <= #Tp WCtrlDataStart;
          WCtrlDataStart_q1 <=  WCtrlDataStart;
          WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;
          WCtrlDataStart_q2 <=  WCtrlDataStart_q1;
 
 
          RStatStart_q1 <= #Tp RStatStart;
          RStatStart_q1 <=  RStatStart;
          RStatStart_q2 <= #Tp RStatStart_q1;
          RStatStart_q2 <=  RStatStart_q1;
 
 
          LatchByte[0] <= #Tp LatchByte0_d;
          LatchByte[0] <=  LatchByte0_d;
          LatchByte[1] <= #Tp LatchByte1_d;
          LatchByte[1] <=  LatchByte1_d;
 
 
          LatchByte0_d <= #Tp LatchByte0_d2;
          LatchByte0_d <=  LatchByte0_d2;
          LatchByte1_d <= #Tp LatchByte1_d2;
          LatchByte1_d <=  LatchByte1_d2;
 
 
          InProgress_q1 <= #Tp InProgress;
          InProgress_q1 <=  InProgress;
          InProgress_q2 <= #Tp InProgress_q1;
          InProgress_q2 <=  InProgress_q1;
          InProgress_q3 <= #Tp InProgress_q2;
          InProgress_q3 <=  InProgress_q2;
        end
        end
    end
    end
end
end
 
 
 
 
Line 363... Line 361...
// Generation of the WriteOp signal (indicates when a write is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      InProgress <= #Tp 1'b0;
      InProgress <=  1'b0;
      WriteOp <= #Tp 1'b0;
      WriteOp <=  1'b0;
    end
    end
  else
  else
    begin
    begin
      if(MdcEn)
      if(MdcEn)
        begin
        begin
          if(StartOp)
          if(StartOp)
            begin
            begin
              if(~InProgress)
              if(~InProgress)
                WriteOp <= #Tp WriteDataOp;
                WriteOp <=  WriteDataOp;
              InProgress <= #Tp 1'b1;
              InProgress <=  1'b1;
            end
            end
          else
          else
            begin
            begin
              if(EndOp)
              if(EndOp)
                begin
                begin
                  InProgress <= #Tp 1'b0;
                  InProgress <=  1'b0;
                  WriteOp <= #Tp 1'b0;
                  WriteOp <=  1'b0;
                end
                end
            end
            end
        end
        end
    end
    end
end
end
Line 394... Line 392...
 
 
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    BitCounter[6:0] <= #Tp 7'h0;
    BitCounter[6:0] <=  7'h0;
  else
  else
    begin
    begin
      if(MdcEn)
      if(MdcEn)
        begin
        begin
          if(InProgress)
          if(InProgress)
            begin
            begin
              if(NoPre & ( BitCounter == 7'h0 ))
              if(NoPre & ( BitCounter == 7'h0 ))
                BitCounter[6:0] <= #Tp 7'h21;
                BitCounter[6:0] <=  7'h21;
              else
              else
                BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;
                BitCounter[6:0] <=  BitCounter[6:0] + 1'b1;
            end
            end
          else
          else
            BitCounter[6:0] <= #Tp 7'h0;
            BitCounter[6:0] <=  7'h0;
        end
        end
    end
    end
end
end
 
 
 
 
Line 428... Line 426...
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
 
 
 
 
// Connecting the Clock Generator Module
// Connecting the Clock Generator Module
eth_clockgen #(.Tp(Tp))
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
 
                   );
                   );
 
 
// Connecting the Shift Register Module
// Connecting the Shift Register Module
eth_shiftreg #(.Tp(Tp))
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
 
                    .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
                    .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
                    .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
                    .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
                   );
                   );
 
 
// Connecting the Output Control Module
// Connecting the Output Control Module
eth_outputcontrol #(.Tp(Tp))
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
 
                          .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
                          .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
                          .Mdo(Mdo), .MdoEn(MdoEn)
                          .Mdo(Mdo), .MdoEn(MdoEn)
                         );
                         );
 
 
endmodule
endmodule

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