| Line 133... |
Line 133... |
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output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
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output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
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output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
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output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
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output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
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output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
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parameter Tp = 1;
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reg Nvalid;
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reg Nvalid;
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reg EndBusy_d; // Pre-end Busy signal
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reg EndBusy_d; // Pre-end Busy signal
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reg EndBusy; // End Busy signal (stops the operation in progress)
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reg EndBusy; // End Busy signal (stops the operation in progress)
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| Line 196... |
Line 194... |
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
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// Generation of the EndBusy signal. It is used for ending the MII Management operation.
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
|
if(Reset)
|
begin
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begin
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EndBusy_d <= #Tp 1'b0;
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EndBusy_d <= 1'b0;
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EndBusy <= #Tp 1'b0;
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EndBusy <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;
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EndBusy_d <= ~InProgress_q2 & InProgress_q3;
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EndBusy <= #Tp EndBusy_d;
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EndBusy <= EndBusy_d;
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end
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end
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end
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end
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// Update MII RX_DATA register
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// Update MII RX_DATA register
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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UpdateMIIRX_DATAReg <= #Tp 0;
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UpdateMIIRX_DATAReg <= 0;
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else
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else
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if(EndBusy & ~WCtrlDataStart_q)
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if(EndBusy & ~WCtrlDataStart_q)
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UpdateMIIRX_DATAReg <= #Tp 1;
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UpdateMIIRX_DATAReg <= 1;
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else
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else
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UpdateMIIRX_DATAReg <= #Tp 0;
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UpdateMIIRX_DATAReg <= 0;
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end
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end
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// Generation of the delayed signals used for positive edge triggering.
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// Generation of the delayed signals used for positive edge triggering.
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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begin
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begin
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WCtrlData_q1 <= #Tp 1'b0;
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WCtrlData_q1 <= 1'b0;
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WCtrlData_q2 <= #Tp 1'b0;
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WCtrlData_q2 <= 1'b0;
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WCtrlData_q3 <= #Tp 1'b0;
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WCtrlData_q3 <= 1'b0;
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RStat_q1 <= #Tp 1'b0;
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RStat_q1 <= 1'b0;
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RStat_q2 <= #Tp 1'b0;
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RStat_q2 <= 1'b0;
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RStat_q3 <= #Tp 1'b0;
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RStat_q3 <= 1'b0;
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ScanStat_q1 <= #Tp 1'b0;
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ScanStat_q1 <= 1'b0;
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ScanStat_q2 <= #Tp 1'b0;
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ScanStat_q2 <= 1'b0;
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SyncStatMdcEn <= #Tp 1'b0;
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SyncStatMdcEn <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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WCtrlData_q1 <= #Tp WCtrlData;
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WCtrlData_q1 <= WCtrlData;
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WCtrlData_q2 <= #Tp WCtrlData_q1;
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WCtrlData_q2 <= WCtrlData_q1;
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WCtrlData_q3 <= #Tp WCtrlData_q2;
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WCtrlData_q3 <= WCtrlData_q2;
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RStat_q1 <= #Tp RStat;
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RStat_q1 <= RStat;
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RStat_q2 <= #Tp RStat_q1;
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RStat_q2 <= RStat_q1;
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RStat_q3 <= #Tp RStat_q2;
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RStat_q3 <= RStat_q2;
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ScanStat_q1 <= #Tp ScanStat;
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ScanStat_q1 <= ScanStat;
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ScanStat_q2 <= #Tp ScanStat_q1;
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ScanStat_q2 <= ScanStat_q1;
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if(MdcEn)
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if(MdcEn)
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SyncStatMdcEn <= #Tp ScanStat_q2;
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SyncStatMdcEn <= ScanStat_q2;
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end
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end
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end
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end
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// Generation of the Start Commands (Write Control Data or Read Status)
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// Generation of the Start Commands (Write Control Data or Read Status)
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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begin
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begin
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WCtrlDataStart <= #Tp 1'b0;
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WCtrlDataStart <= 1'b0;
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WCtrlDataStart_q <= #Tp 1'b0;
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WCtrlDataStart_q <= 1'b0;
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RStatStart <= #Tp 1'b0;
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RStatStart <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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if(EndBusy)
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if(EndBusy)
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begin
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begin
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WCtrlDataStart <= #Tp 1'b0;
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WCtrlDataStart <= 1'b0;
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RStatStart <= #Tp 1'b0;
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RStatStart <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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if(WCtrlData_q2 & ~WCtrlData_q3)
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if(WCtrlData_q2 & ~WCtrlData_q3)
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WCtrlDataStart <= #Tp 1'b1;
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WCtrlDataStart <= 1'b1;
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if(RStat_q2 & ~RStat_q3)
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if(RStat_q2 & ~RStat_q3)
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RStatStart <= #Tp 1'b1;
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RStatStart <= 1'b1;
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WCtrlDataStart_q <= #Tp WCtrlDataStart;
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WCtrlDataStart_q <= WCtrlDataStart;
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end
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end
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end
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end
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end
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end
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// Generation of the Nvalid signal (indicates when the status is invalid)
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// Generation of the Nvalid signal (indicates when the status is invalid)
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
|
begin
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if(Reset)
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if(Reset)
|
Nvalid <= #Tp 1'b0;
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Nvalid <= 1'b0;
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else
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else
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begin
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begin
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if(~InProgress_q2 & InProgress_q3)
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if(~InProgress_q2 & InProgress_q3)
|
begin
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begin
|
Nvalid <= #Tp 1'b0;
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Nvalid <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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if(ScanStat_q2 & ~SyncStatMdcEn)
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if(ScanStat_q2 & ~SyncStatMdcEn)
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Nvalid <= #Tp 1'b1;
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Nvalid <= 1'b1;
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end
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end
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end
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end
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end
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end
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|
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// Signals used for the generation of the Operation signals (positive edge)
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// Signals used for the generation of the Operation signals (positive edge)
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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begin
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begin
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WCtrlDataStart_q1 <= #Tp 1'b0;
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WCtrlDataStart_q1 <= 1'b0;
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WCtrlDataStart_q2 <= #Tp 1'b0;
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WCtrlDataStart_q2 <= 1'b0;
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RStatStart_q1 <= #Tp 1'b0;
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RStatStart_q1 <= 1'b0;
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RStatStart_q2 <= #Tp 1'b0;
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RStatStart_q2 <= 1'b0;
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InProgress_q1 <= #Tp 1'b0;
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InProgress_q1 <= 1'b0;
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InProgress_q2 <= #Tp 1'b0;
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InProgress_q2 <= 1'b0;
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InProgress_q3 <= #Tp 1'b0;
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InProgress_q3 <= 1'b0;
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LatchByte0_d <= #Tp 1'b0;
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LatchByte0_d <= 1'b0;
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LatchByte1_d <= #Tp 1'b0;
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LatchByte1_d <= 1'b0;
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|
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LatchByte <= #Tp 2'b00;
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LatchByte <= 2'b00;
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end
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end
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else
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else
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begin
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begin
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if(MdcEn)
|
if(MdcEn)
|
begin
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begin
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WCtrlDataStart_q1 <= #Tp WCtrlDataStart;
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WCtrlDataStart_q1 <= WCtrlDataStart;
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WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;
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WCtrlDataStart_q2 <= WCtrlDataStart_q1;
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RStatStart_q1 <= #Tp RStatStart;
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RStatStart_q1 <= RStatStart;
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RStatStart_q2 <= #Tp RStatStart_q1;
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RStatStart_q2 <= RStatStart_q1;
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|
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LatchByte[0] <= #Tp LatchByte0_d;
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LatchByte[0] <= LatchByte0_d;
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LatchByte[1] <= #Tp LatchByte1_d;
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LatchByte[1] <= LatchByte1_d;
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|
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LatchByte0_d <= #Tp LatchByte0_d2;
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LatchByte0_d <= LatchByte0_d2;
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LatchByte1_d <= #Tp LatchByte1_d2;
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LatchByte1_d <= LatchByte1_d2;
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|
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InProgress_q1 <= #Tp InProgress;
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InProgress_q1 <= InProgress;
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InProgress_q2 <= #Tp InProgress_q1;
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InProgress_q2 <= InProgress_q1;
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InProgress_q3 <= #Tp InProgress_q2;
|
InProgress_q3 <= InProgress_q2;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
| Line 363... |
Line 361... |
// Generation of the WriteOp signal (indicates when a write is in progress)
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
InProgress <= #Tp 1'b0;
|
InProgress <= 1'b0;
|
WriteOp <= #Tp 1'b0;
|
WriteOp <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(MdcEn)
|
if(MdcEn)
|
begin
|
begin
|
if(StartOp)
|
if(StartOp)
|
begin
|
begin
|
if(~InProgress)
|
if(~InProgress)
|
WriteOp <= #Tp WriteDataOp;
|
WriteOp <= WriteDataOp;
|
InProgress <= #Tp 1'b1;
|
InProgress <= 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(EndOp)
|
if(EndOp)
|
begin
|
begin
|
InProgress <= #Tp 1'b0;
|
InProgress <= 1'b0;
|
WriteOp <= #Tp 1'b0;
|
WriteOp <= 1'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
| Line 394... |
Line 392... |
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BitCounter[6:0] <= #Tp 7'h0;
|
BitCounter[6:0] <= 7'h0;
|
else
|
else
|
begin
|
begin
|
if(MdcEn)
|
if(MdcEn)
|
begin
|
begin
|
if(InProgress)
|
if(InProgress)
|
begin
|
begin
|
if(NoPre & ( BitCounter == 7'h0 ))
|
if(NoPre & ( BitCounter == 7'h0 ))
|
BitCounter[6:0] <= #Tp 7'h21;
|
BitCounter[6:0] <= 7'h21;
|
else
|
else
|
BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;
|
BitCounter[6:0] <= BitCounter[6:0] + 1'b1;
|
end
|
end
|
else
|
else
|
BitCounter[6:0] <= #Tp 7'h0;
|
BitCounter[6:0] <= 7'h0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
| Line 428... |
Line 426... |
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
|
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
|
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
|
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
|
|
|
|
|
// Connecting the Clock Generator Module
|
// Connecting the Clock Generator Module
|
eth_clockgen #(.Tp(Tp))
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|
);
|
);
|
|
|
// Connecting the Shift Register Module
|
// Connecting the Shift Register Module
|
eth_shiftreg #(.Tp(Tp))
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
);
|
);
|
|
|
// Connecting the Output Control Module
|
// Connecting the Output Control Module
|
eth_outputcontrol #(.Tp(Tp))
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
