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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_macstatus.v] - Diff between revs 346 and 352

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Rev 346 Rev 352
Line 124... Line 124...
                      r_FullD
                      r_FullD
                    );
                    );
 
 
 
 
 
 
parameter Tp = 1;
 
 
 
 
 
input         MRxClk;
input         MRxClk;
input         Reset;
input         Reset;
input         RxCrcError;
input         RxCrcError;
input         MRxErr;
input         MRxErr;
Line 203... Line 201...
 
 
// Crc error
// Crc error
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    LatchedCrcError <=#Tp 1'b0;
    LatchedCrcError <= 1'b0;
  else
  else
  if(RxStateSFD)
  if(RxStateSFD)
    LatchedCrcError <=#Tp 1'b0;
    LatchedCrcError <= 1'b0;
  else
  else
  if(RxStateData[0])
  if(RxStateData[0])
    LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
    LatchedCrcError <= RxCrcError & ~RxByteCntEq0;
end
end
 
 
 
 
// LatchedMRxErr
// LatchedMRxErr
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    LatchedMRxErr <=#Tp 1'b0;
    LatchedMRxErr <= 1'b0;
  else
  else
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
    LatchedMRxErr <=#Tp 1'b1;
    LatchedMRxErr <= 1'b1;
  else
  else
    LatchedMRxErr <=#Tp 1'b0;
    LatchedMRxErr <= 1'b0;
end
end
 
 
 
 
// ReceivedPacketGood
// ReceivedPacketGood
assign ReceivedPacketGood = ~LatchedCrcError;
assign ReceivedPacketGood = ~LatchedCrcError;
Line 247... Line 245...
 
 
// LoadRxStatus
// LoadRxStatus
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    LoadRxStatus <=#Tp 1'b0;
    LoadRxStatus <= 1'b0;
  else
  else
    LoadRxStatus <=#Tp TakeSample;
    LoadRxStatus <= TakeSample;
end
end
 
 
 
 
 
 
// ReceiveEnd
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    ReceiveEnd  <=#Tp 1'b0;
    ReceiveEnd  <= 1'b0;
  else
  else
    ReceiveEnd  <=#Tp LoadRxStatus;
    ReceiveEnd  <= LoadRxStatus;
end
end
 
 
 
 
// Invalid Symbol received during 100Mbps mode
// Invalid Symbol received during 100Mbps mode
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
Line 272... Line 270...
 
 
// InvalidSymbol
// InvalidSymbol
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    InvalidSymbol <=#Tp 1'b0;
    InvalidSymbol <= 1'b0;
  else
  else
  if(LoadRxStatus & ~SetInvalidSymbol)
  if(LoadRxStatus & ~SetInvalidSymbol)
    InvalidSymbol <=#Tp 1'b0;
    InvalidSymbol <= 1'b0;
  else
  else
  if(SetInvalidSymbol)
  if(SetInvalidSymbol)
    InvalidSymbol <=#Tp 1'b1;
    InvalidSymbol <= 1'b1;
end
end
 
 
 
 
// Late Collision
// Late Collision
 
 
Line 290... Line 288...
reg RxColWindow;
reg RxColWindow;
// Collision Window
// Collision Window
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RxLateCollision <=#Tp 1'b0;
    RxLateCollision <= 1'b0;
  else
  else
  if(LoadRxStatus)
  if(LoadRxStatus)
    RxLateCollision <=#Tp 1'b0;
    RxLateCollision <= 1'b0;
  else
  else
  if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
  if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
    RxLateCollision <=#Tp 1'b1;
    RxLateCollision <= 1'b1;
end
end
 
 
// Collision Window
// Collision Window
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RxColWindow <=#Tp 1'b1;
    RxColWindow <= 1'b1;
  else
  else
  if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
  if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
    RxColWindow <=#Tp 1'b0;
    RxColWindow <= 1'b0;
  else
  else
  if(RxStateIdle)
  if(RxStateIdle)
    RxColWindow <=#Tp 1'b1;
    RxColWindow <= 1'b1;
end
end
 
 
 
 
// ShortFrame
// ShortFrame
reg ShortFrame;
reg ShortFrame;
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    ShortFrame <=#Tp 1'b0;
    ShortFrame <= 1'b0;
  else
  else
  if(LoadRxStatus)
  if(LoadRxStatus)
    ShortFrame <=#Tp 1'b0;
    ShortFrame <= 1'b0;
  else
  else
  if(TakeSample)
  if(TakeSample)
    ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
    ShortFrame <= RxByteCnt[15:0] < r_MinFL[15:0];
end
end
 
 
 
 
// DribbleNibble
// DribbleNibble
reg DribbleNibble;
reg DribbleNibble;
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    DribbleNibble <=#Tp 1'b0;
    DribbleNibble <= 1'b0;
  else
  else
  if(RxStateSFD)
  if(RxStateSFD)
    DribbleNibble <=#Tp 1'b0;
    DribbleNibble <= 1'b0;
  else
  else
  if(~MRxDV & RxStateData[1])
  if(~MRxDV & RxStateData[1])
    DribbleNibble <=#Tp 1'b1;
    DribbleNibble <= 1'b1;
end
end
 
 
 
 
reg ReceivedPacketTooBig;
reg ReceivedPacketTooBig;
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    ReceivedPacketTooBig <=#Tp 1'b0;
    ReceivedPacketTooBig <= 1'b0;
  else
  else
  if(LoadRxStatus)
  if(LoadRxStatus)
    ReceivedPacketTooBig <=#Tp 1'b0;
    ReceivedPacketTooBig <= 1'b0;
  else
  else
  if(TakeSample)
  if(TakeSample)
    ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
    ReceivedPacketTooBig <= ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
end
 
 
 
 
 
 
// Latched Retry counter for tx status
// Latched Retry counter for tx status
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RetryCntLatched <=#Tp 4'h0;
    RetryCntLatched <= 4'h0;
  else
  else
  if(StartTxDone | StartTxAbort)
  if(StartTxDone | StartTxAbort)
    RetryCntLatched <=#Tp RetryCnt;
    RetryCntLatched <= RetryCnt;
end
end
 
 
 
 
// Latched Retransmission limit
// Latched Retransmission limit
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RetryLimit <=#Tp 1'h0;
    RetryLimit <= 1'h0;
  else
  else
  if(StartTxDone | StartTxAbort)
  if(StartTxDone | StartTxAbort)
    RetryLimit <=#Tp MaxCollisionOccured;
    RetryLimit <= MaxCollisionOccured;
end
end
 
 
 
 
// Latched Late Collision
// Latched Late Collision
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    LateCollLatched <=#Tp 1'b0;
    LateCollLatched <= 1'b0;
  else
  else
  if(StartTxDone | StartTxAbort)
  if(StartTxDone | StartTxAbort)
    LateCollLatched <=#Tp LateCollision;
    LateCollLatched <= LateCollision;
end
end
 
 
 
 
 
 
// Latched Defer state
// Latched Defer state
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    DeferLatched <=#Tp 1'b0;
    DeferLatched <= 1'b0;
  else
  else
  if(DeferIndication)
  if(DeferIndication)
    DeferLatched <=#Tp 1'b1;
    DeferLatched <= 1'b1;
  else
  else
  if(RstDeferLatched)
  if(RstDeferLatched)
    DeferLatched <=#Tp 1'b0;
    DeferLatched <= 1'b0;
end
end
 
 
 
 
// CarrierSenseLost
// CarrierSenseLost
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    CarrierSenseLost <=#Tp 1'b0;
    CarrierSenseLost <= 1'b0;
  else
  else
  if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
  if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
    CarrierSenseLost <=#Tp 1'b1;
    CarrierSenseLost <= 1'b1;
  else
  else
  if(TxStartFrm)
  if(TxStartFrm)
    CarrierSenseLost <=#Tp 1'b0;
    CarrierSenseLost <= 1'b0;
end
end
 
 
 
 
endmodule
endmodule
 
 
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