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[/] [pairing/] [trunk/] [testbench/] [test_f3m_inv.v] - Blame information for rev 22

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1 4 homer.xing
`timescale 1ns / 1ps
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`define CLOCK_PERIOD 10
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module test_f3m_inv;
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    // Inputs
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    reg [193:0] A;
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    reg clk;
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    reg reset;
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    // Outputs
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    wire [193:0] C;
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    wire done;
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    // Instantiate the Unit Under Test (UUT)
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    f3m_inv uut (
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        .A(A),
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        .clk(clk),
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        .reset(reset),
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        .C(C),
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        .done(done)
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    );
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    always #`CLOCK_PERIOD clk = ~clk;
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    initial begin
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        // Initialize Inputs
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        A = 0;
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        clk = 0;
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        reset = 0;
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        // Wait 100 ns for global reset to finish
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        #100;
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        // Add stimulus here
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        A = 32'b10_01_01_10_01_00; // A = "x";
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        @(negedge clk); reset = 1;
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        @(negedge clk); reset = 0;
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        #(200*2*`CLOCK_PERIOD);
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        if (C != 192'h65450169824811252a919a8a02964184221a1562655252a9) $display("Error!");
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        $display("Good!"); $finish;
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    end
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endmodule
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