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[/] [pairing/] [trunk/] [testbench/] [test_f32m_mult.v] - Blame information for rev 22

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1 4 homer.xing
`timescale 1ns / 1ps
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module test_f32m_mult;
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5 22 homer.xing
    // Inputs
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    reg reset;
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    reg clk;
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    reg [387:0] a,b;
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10 22 homer.xing
    // Outputs
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    wire [387:0] c;
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    wire done;
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14 22 homer.xing
    // Instantiate the Unit Under Test (UUT)
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    f32m_mult uut (
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        .reset(reset),
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        .clk(clk),
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        .a(a),
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        .b(b),
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        .c(c),
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        .done(done)
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    );
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24 22 homer.xing
    initial begin
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        // Initialize Inputs
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        reset = 0;
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        clk = 0;
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        a = 0;
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        b = 0;
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        // Wait 100 ns for global reset to finish
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        #100;
33 4 homer.xing
 
34 22 homer.xing
        // Add stimulus here
35 4 homer.xing
        a={194'h2a8aa25aa245066106a40806618aa88a2946881162a864652,194'h28258889288590a464559a0854a0a269820495a6069969aa2};
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        b={194'h59a0a46891951042640592a2969888012108059214504048,194'h55812555968918122622106514a25488204895614889112};
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        @ (negedge clk) reset = 1;
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        @ (negedge clk) reset = 0;
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        @ (posedge done);
40 7 homer.xing
        if (c!=={194'h9594010a580186621a840406105460622891085122060a45,194'h59a1595621295a89260802a045194a96050a6202164000a9}) $display("E1");
41 4 homer.xing
        #100;
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        a={194'h8864990666a959a88500249a244495aaa26a2a0194082aa1,194'h2a9481526946468065456052045865262520a4a9520a5a665};
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        b={194'h116698585aa229805611194a6520151245204aa9114a89200,194'h8855225a25520a048a912141800501862189941946906540};
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        @ (negedge clk) reset = 1;
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        @ (negedge clk) reset = 0;
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        @ (posedge done);
48 7 homer.xing
        if (c!=={194'h215608121442a91950aaa59514a9486258684486825840894,194'h284845aa0664918068988811691a290658228028985249a48}) $display("E2");
49 4 homer.xing
        #100;
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        $finish;
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    end
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    always #5 clk = ~clk;
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endmodule
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