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[/] [pairing/] [trunk/] [rtl/] [f3m.v] - Blame information for rev 7

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1 2 homer.xing
`include "inc.v"
2
`define MOST 2*`M+1:2*`M
3
 
4 3 homer.xing
// out = (v1 & l1) | (v2 & l2)
5
module f3m_mux2(v1, l1, v2, l2, out);
6
    input [`WIDTH:0] v1, v2;
7
    input l1, l2;
8
    output [`WIDTH:0] out;
9
    genvar i;
10
    generate
11
        for(i=0;i<=`WIDTH;i=i+1)
12
          begin : label
13
            assign out[i] = (v1[i] & l1) | (v2[i] & l2);
14
          end
15
    endgenerate
16
endmodule
17
 
18
// out = (v1 & l1) | (v2 & l2) | (v3 & l3)
19
module f3m_mux3(v1, l1, v2, l2, v3, l3, out);
20
    input [`WIDTH:0] v1, v2, v3;
21
    input l1, l2, l3;
22
    output [`WIDTH:0] out;
23
    genvar i;
24
    generate
25
        for(i=0;i<=`WIDTH;i=i+1)
26
          begin : label
27
            assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
28
          end
29
    endgenerate
30
endmodule
31
 
32
// out = (v0 & l0) | (v1 & l1) | (v2 & l2) | ... | (v5 & l5)
33
module f3m_mux6(v0, v1, v2, v3, v4, v5, l0, l1, l2, l3, l4, l5, out);
34
    input l0, l1, l2, l3, l4, l5;
35
    input [`WIDTH:0] v0, v1, v2, v3, v4, v5;
36
    output reg [`WIDTH:0] out;
37
    always @ (l0,l1,l2,l3,l4,l5,v0,v1,v2,v3,v4,v5)
38
      case ({l0,l1,l2,l3,l4,l5})
39
        6'b100000: out = v0;
40
        6'b010000: out = v1;
41
        6'b001000: out = v2;
42
        6'b000100: out = v3;
43
        6'b000010: out = v4;
44
        6'b000001: out = v5;
45
        default: out = 0;
46
      endcase
47
endmodule
48
 
49 2 homer.xing
// f3m_add: C = A + B, in field F_{3^M}
50
module f3m_add(A, B, C);
51
    input [`WIDTH : 0] A, B;
52
    output [`WIDTH : 0] C;
53
    genvar i;
54
    generate
55
        for(i=0; i<`M; i=i+1) begin: aa
56
            f3_add aa(A[(2*i+1) : 2*i], B[(2*i+1) : 2*i], C[(2*i+1) : 2*i]);
57
        end
58
    endgenerate
59
endmodule
60
 
61 3 homer.xing
// f3m_add3: c == a0+a1+a2, in field GF(3^M)
62
module f3m_add3(a0, a1, a2, c);
63
    input [`WIDTH:0] a0,a1,a2;
64
    output [`WIDTH:0] c;
65
    wire [`WIDTH:0] v;
66
    f3m_add
67
        ins1 (a0,a1,v), // v == a0+a1
68
        ins2 (v,a2,c);  // c == v+a2 == a0+a1+a2
69
endmodule
70
 
71
// f3m_add4: c == a0+a1+a2+a3, in field GF(3^M)
72
module f3m_add4(a0, a1, a2, a3, c);
73
    input [`WIDTH:0] a0,a1,a2,a3;
74
    output [`WIDTH:0] c;
75
    wire [`WIDTH:0] v1,v2;
76
    f3m_add
77
        ins1 (a0,a1,v1), // v1 == a0+a1
78
        ins2 (a2,a3,v2), // v2 == a2+a3
79
        ins3 (v1,v2,c);  // c == v1+v2 == a0+a1+a2+a3
80
endmodule
81
 
82 2 homer.xing
// f3m_neg: c == -a in GF(3^M)
83
module f3m_neg(a, c);
84
    input [`WIDTH:0] a;
85
    output [`WIDTH:0] c;
86
    genvar i;
87
    generate
88
        for(i=0;i<=`WIDTH;i=i+2)
89
          begin:label
90
            assign c[i+1:i] = {a[i],a[i+1]};
91
          end
92
    endgenerate
93
endmodule
94
 
95
// f3m_sub: C = A - B, in field F_{3^M}
96
module f3m_sub(A, B, C);
97
    input [`WIDTH : 0] A, B;
98
    output [`WIDTH : 0] C;
99
    genvar i;
100
    generate
101
        for(i=0; i<`M; i=i+1) begin: aa
102
            f3_sub aa(A[(2*i+1) : 2*i], B[(2*i+1) : 2*i], C[(2*i+1) : 2*i]);
103
        end
104
    endgenerate
105
endmodule
106
 
107
// f3m_mult: C = A * B, in field GF(3^M)
108
module f3m_mult(clk, reset, A, B, C, done);
109
    input [`WIDTH : 0] A, B;
110
    input clk;
111
    input reset;
112
    output reg [`WIDTH : 0] C;
113
    output reg done;
114
    reg [`WIDTH : 0] x, y, z;
115
    wire [`WIDTH : 0] z1, z2, z4;
116
    wire [`WIDTH+2 : 0] z3;
117
    reg [`M+1 : 0] i;
118
    wire [`M+1 : 0] i1;
119
    wire done1;
120
    wire [1:0] dummy;
121
 
122
    func4
123
        ins1 ({2'b0,x}, y[1:0], {dummy,z1}); // z1 == A * B[0]
124
    f3m_add
125
        ins2 (z1, z, z2); // z2 == z1 + z == A*B[0] + z
126
    assign z4 = {2'd0, y[`WIDTH:2]}; // z4 == y >> 2
127
    func3
128
        ins3 ({2'd0,x}, z3); // z3 == X*x mod p(x)
129
    assign i1 = {1'b0, i[`M+1:1]}; // i1 == i >> 1
130
    assign done1 = (i1[1:0] == 2'b01);
131
 
132
    always @ (posedge clk)
133
        if (done1)
134
          begin
135
            C <= z;
136
          end
137
 
138
    always @ (posedge clk)
139
        if (reset)
140
            done <= 0;
141
        else if (done1)
142
            done <= 1;
143
 
144
    always @ (posedge clk)
145
      begin
146
        if (reset)
147
          begin
148
            x <= A; y <= B; z <= 0; i <= ~0;
149
          end
150
        else
151
          begin
152
            x <= z3[`WIDTH:0]; y <= z4; z <= z2; i <= i1;
153
          end
154
      end
155
endmodule
156
 
157 7 homer.xing
// c0 == a0*b0; c1 == a1*b1; c2 == a2*b2; all in GF(3^M)
158
module f3m_mult3(clk, reset,
159
                 a0, b0, c0,
160
                 a1, b1, c1,
161
                 a2, b2, c2,
162
                 done);
163
    input clk, reset;
164
    input [`WIDTH:0] a0, b0, a1, b1, a2, b2;
165
    output reg [`WIDTH:0] c0, c1, c2;
166
    output reg done;
167
    reg [3:0] K;
168
    reg mult_reset, delay1, delay2;
169
    wire e1, e2, e3, mult_done, delay3, rst;
170
    wire [`WIDTH:0] in1, in2, o;
171
 
172
    assign rst = delay2;
173
    assign {e1,e2,e3} = K[3:1];
174
 
175
    f3m_mux3
176
        ins9 (a0, e1, a1, e2, a2, e3, in1),
177
        ins10 (b0, e1, b1, e2, b2, e3, in2);
178
    f3m_mult
179
        ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2 in GF(3^m)
180
    func6
181
        ins12 (clk, mult_done, delay3);
182
 
183
    always @ (posedge clk)
184
      begin
185
        if (e1) c0 <= o;
186
        if (e2) c1 <= o;
187
        if (e3) c2 <= o;
188
      end
189
 
190
    always @ (posedge clk)
191
        if (reset) K <= 4'b1000;
192
        else if (delay3) K <= {1'b0,K[3:1]};
193
 
194
    always @ (posedge clk)
195
      begin
196
        if (rst) mult_reset <= 1;
197
        else if (mult_done) mult_reset <= 1;
198
        else mult_reset <= 0;
199
      end
200
 
201
    always @ (posedge clk)
202
        if (reset)     done <= 0;
203
        else if (K[0]) done <= 1;
204
 
205
    always @ (posedge clk)
206
      begin
207
        delay2 <= delay1; delay1 <= reset;
208
      end
209
endmodule
210
 
211 2 homer.xing
/* out == in^3 mod p(x) */
212
/* p(x) == x^97 + x^12 + 2 */
213
module f3m_cubic(input [193:0] in, output [193:0] out);
214
wire [1:0] w0; f3_add a0(in[131:130], in[139:138], w0);
215
wire [1:0] w1; f3_add a1(in[133:132], in[141:140], w1);
216
wire [1:0] w2; f3_add a2(in[135:134], in[143:142], w2);
217
wire [1:0] w3; f3_add a3(in[137:136], in[145:144], w3);
218
wire [1:0] w4; f3_add a4(in[147:146], in[155:154], w4);
219
wire [1:0] w5; f3_add a5(in[149:148], in[157:156], w5);
220
wire [1:0] w6; f3_add a6(in[151:150], in[159:158], w6);
221
wire [1:0] w7; f3_add a7(in[153:152], in[161:160], w7);
222
wire [1:0] w8; f3_add a8(in[163:162], in[171:170], w8);
223
wire [1:0] w9; f3_add a9(in[165:164], in[173:172], w9);
224
wire [1:0] w10; f3_add a10(in[167:166], in[175:174], w10);
225
wire [1:0] w11; f3_add a11(in[169:168], in[177:176], w11);
226
wire [1:0] w12; f3_add a12(in[179:178], in[187:186], w12);
227
wire [1:0] w13; f3_add a13(in[181:180], in[189:188], w13);
228
wire [1:0] w14; f3_add a14(in[183:182], in[191:190], w14);
229
wire [1:0] w15; f3_add a15(in[185:184], in[193:192], w15);
230
wire [1:0] w16;
231
f3_add a16(in[1:0], w12, w16);
232
assign out[1:0] = w16;
233
wire [1:0] w17;
234
f3_add a17({in[122],in[123]}, in[131:130], w17);
235
assign out[3:2] = w17;
236
assign out[5:4] = in[67:66];
237
wire [1:0] w18;
238
f3_add a18(in[3:2], w13, w18);
239
assign out[7:6] = w18;
240
wire [1:0] w19;
241
f3_add a19({in[124],in[125]}, in[133:132], w19);
242
assign out[9:8] = w19;
243
assign out[11:10] = in[69:68];
244
wire [1:0] w20;
245
f3_add a20(in[5:4], w14, w20);
246
assign out[13:12] = w20;
247
wire [1:0] w21;
248
f3_add a21({in[126],in[127]}, in[135:134], w21);
249
assign out[15:14] = w21;
250
assign out[17:16] = in[71:70];
251
wire [1:0] w22;
252
f3_add a22(in[7:6], w15, w22);
253
assign out[19:18] = w22;
254
wire [1:0] w23;
255
f3_add a23({in[128],in[129]}, in[137:136], w23);
256
assign out[21:20] = w23;
257
assign out[23:22] = in[73:72];
258
wire [1:0] w24;
259
f3_add a24(in[9:8], {in[178],in[179]}, w24);
260
assign out[25:24] = w24;
261
wire [1:0] w25;
262
f3_add a25(in[123:122], w0, w25);
263
assign out[27:26] = w25;
264
wire [1:0] w26;
265
f3_add a26({in[66],in[67]}, in[75:74], w26);
266
assign out[29:28] = w26;
267
wire [1:0] w27;
268
f3_add a27(in[11:10], {in[180],in[181]}, w27);
269
assign out[31:30] = w27;
270
wire [1:0] w28;
271
f3_add a28(in[125:124], w1, w28);
272
assign out[33:32] = w28;
273
wire [1:0] w29;
274
f3_add a29({in[68],in[69]}, in[77:76], w29);
275
assign out[35:34] = w29;
276
wire [1:0] w30;
277
f3_add a30(in[13:12], {in[182],in[183]}, w30);
278
assign out[37:36] = w30;
279
wire [1:0] w31;
280
f3_add a31(in[127:126], w2, w31);
281
assign out[39:38] = w31;
282
wire [1:0] w32;
283
f3_add a32({in[70],in[71]}, in[79:78], w32);
284
assign out[41:40] = w32;
285
wire [1:0] w33;
286
f3_add a33(in[15:14], {in[184],in[185]}, w33);
287
assign out[43:42] = w33;
288
wire [1:0] w34;
289
f3_add a34(in[129:128], w3, w34);
290
assign out[45:44] = w34;
291
wire [1:0] w35;
292
f3_add a35({in[72],in[73]}, in[81:80], w35);
293
assign out[47:46] = w35;
294
wire [1:0] w36;
295
f3_add a36(in[17:16], {in[186],in[187]}, w36);
296
assign out[49:48] = w36;
297
wire [1:0] w37;
298
f3_add a37(in[147:146], w0, w37);
299
assign out[51:50] = w37;
300
wire [1:0] w38;
301
f3_add a38({in[74],in[75]}, in[83:82], w38);
302
assign out[53:52] = w38;
303
wire [1:0] w39;
304
f3_add a39(in[19:18], {in[188],in[189]}, w39);
305
assign out[55:54] = w39;
306
wire [1:0] w40;
307
f3_add a40(in[149:148], w1, w40);
308
assign out[57:56] = w40;
309
wire [1:0] w41;
310
f3_add a41({in[76],in[77]}, in[85:84], w41);
311
assign out[59:58] = w41;
312
wire [1:0] w42;
313
f3_add a42(in[21:20], {in[190],in[191]}, w42);
314
assign out[61:60] = w42;
315
wire [1:0] w43;
316
f3_add a43(in[151:150], w2, w43);
317
assign out[63:62] = w43;
318
wire [1:0] w44;
319
f3_add a44({in[78],in[79]}, in[87:86], w44);
320
assign out[65:64] = w44;
321
wire [1:0] w45;
322
f3_add a45(in[23:22], {in[192],in[193]}, w45);
323
assign out[67:66] = w45;
324
wire [1:0] w46;
325
f3_add a46(in[153:152], w3, w46);
326
assign out[69:68] = w46;
327
wire [1:0] w47;
328
f3_add a47({in[80],in[81]}, in[89:88], w47);
329
assign out[71:70] = w47;
330
assign out[73:72] = in[25:24];
331
wire [1:0] w48;
332
f3_add a48(in[139:138], w4, w48);
333
assign out[75:74] = w48;
334
wire [1:0] w49;
335
f3_add a49({in[82],in[83]}, in[91:90], w49);
336
assign out[77:76] = w49;
337
assign out[79:78] = in[27:26];
338
wire [1:0] w50;
339
f3_add a50(in[141:140], w5, w50);
340
assign out[81:80] = w50;
341
wire [1:0] w51;
342
f3_add a51({in[84],in[85]}, in[93:92], w51);
343
assign out[83:82] = w51;
344
assign out[85:84] = in[29:28];
345
wire [1:0] w52;
346
f3_add a52(in[143:142], w6, w52);
347
assign out[87:86] = w52;
348
wire [1:0] w53;
349
f3_add a53({in[86],in[87]}, in[95:94], w53);
350
assign out[89:88] = w53;
351
assign out[91:90] = in[31:30];
352
wire [1:0] w54;
353
f3_add a54(in[145:144], w7, w54);
354
assign out[93:92] = w54;
355
wire [1:0] w55;
356
f3_add a55({in[88],in[89]}, in[97:96], w55);
357
assign out[95:94] = w55;
358
assign out[97:96] = in[33:32];
359
wire [1:0] w56;
360
f3_add a56(in[163:162], w4, w56);
361
assign out[99:98] = w56;
362
wire [1:0] w57;
363
f3_add a57({in[90],in[91]}, in[99:98], w57);
364
assign out[101:100] = w57;
365
assign out[103:102] = in[35:34];
366
wire [1:0] w58;
367
f3_add a58(in[165:164], w5, w58);
368
assign out[105:104] = w58;
369
wire [1:0] w59;
370
f3_add a59({in[92],in[93]}, in[101:100], w59);
371
assign out[107:106] = w59;
372
assign out[109:108] = in[37:36];
373
wire [1:0] w60;
374
f3_add a60(in[167:166], w6, w60);
375
assign out[111:110] = w60;
376
wire [1:0] w61;
377
f3_add a61({in[94],in[95]}, in[103:102], w61);
378
assign out[113:112] = w61;
379
assign out[115:114] = in[39:38];
380
wire [1:0] w62;
381
f3_add a62(in[169:168], w7, w62);
382
assign out[117:116] = w62;
383
wire [1:0] w63;
384
f3_add a63({in[96],in[97]}, in[105:104], w63);
385
assign out[119:118] = w63;
386
assign out[121:120] = in[41:40];
387
wire [1:0] w64;
388
f3_add a64(in[155:154], w8, w64);
389
assign out[123:122] = w64;
390
wire [1:0] w65;
391
f3_add a65({in[98],in[99]}, in[107:106], w65);
392
assign out[125:124] = w65;
393
assign out[127:126] = in[43:42];
394
wire [1:0] w66;
395
f3_add a66(in[157:156], w9, w66);
396
assign out[129:128] = w66;
397
wire [1:0] w67;
398
f3_add a67({in[100],in[101]}, in[109:108], w67);
399
assign out[131:130] = w67;
400
assign out[133:132] = in[45:44];
401
wire [1:0] w68;
402
f3_add a68(in[159:158], w10, w68);
403
assign out[135:134] = w68;
404
wire [1:0] w69;
405
f3_add a69({in[102],in[103]}, in[111:110], w69);
406
assign out[137:136] = w69;
407
assign out[139:138] = in[47:46];
408
wire [1:0] w70;
409
f3_add a70(in[161:160], w11, w70);
410
assign out[141:140] = w70;
411
wire [1:0] w71;
412
f3_add a71({in[104],in[105]}, in[113:112], w71);
413
assign out[143:142] = w71;
414
assign out[145:144] = in[49:48];
415
wire [1:0] w72;
416
f3_add a72(in[179:178], w8, w72);
417
assign out[147:146] = w72;
418
wire [1:0] w73;
419
f3_add a73({in[106],in[107]}, in[115:114], w73);
420
assign out[149:148] = w73;
421
assign out[151:150] = in[51:50];
422
wire [1:0] w74;
423
f3_add a74(in[181:180], w9, w74);
424
assign out[153:152] = w74;
425
wire [1:0] w75;
426
f3_add a75({in[108],in[109]}, in[117:116], w75);
427
assign out[155:154] = w75;
428
assign out[157:156] = in[53:52];
429
wire [1:0] w76;
430
f3_add a76(in[183:182], w10, w76);
431
assign out[159:158] = w76;
432
wire [1:0] w77;
433
f3_add a77({in[110],in[111]}, in[119:118], w77);
434
assign out[161:160] = w77;
435
assign out[163:162] = in[55:54];
436
wire [1:0] w78;
437
f3_add a78(in[185:184], w11, w78);
438
assign out[165:164] = w78;
439
wire [1:0] w79;
440
f3_add a79({in[112],in[113]}, in[121:120], w79);
441
assign out[167:166] = w79;
442
assign out[169:168] = in[57:56];
443
wire [1:0] w80;
444
f3_add a80(in[171:170], w12, w80);
445
assign out[171:170] = w80;
446
wire [1:0] w81;
447
f3_add a81({in[114],in[115]}, in[123:122], w81);
448
assign out[173:172] = w81;
449
assign out[175:174] = in[59:58];
450
wire [1:0] w82;
451
f3_add a82(in[173:172], w13, w82);
452
assign out[177:176] = w82;
453
wire [1:0] w83;
454
f3_add a83({in[116],in[117]}, in[125:124], w83);
455
assign out[179:178] = w83;
456
assign out[181:180] = in[61:60];
457
wire [1:0] w84;
458
f3_add a84(in[175:174], w14, w84);
459
assign out[183:182] = w84;
460
wire [1:0] w85;
461
f3_add a85({in[118],in[119]}, in[127:126], w85);
462
assign out[185:184] = w85;
463
assign out[187:186] = in[63:62];
464
wire [1:0] w86;
465
f3_add a86(in[177:176], w15, w86);
466
assign out[189:188] = w86;
467
wire [1:0] w87;
468
f3_add a87({in[120],in[121]}, in[129:128], w87);
469
assign out[191:190] = w87;
470
assign out[193:192] = in[65:64];
471
endmodule
472
 
473
/* nine square in GF(3^m), out = in^9 mod p(x) */
474
/* p(x) == x^97 + x^12 + 2 */
475
module f3m_nine(clk, in, out);
476
    input clk;
477
    input [`WIDTH:0] in;
478
    output reg [`WIDTH:0] out;
479
    wire [`WIDTH:0] a,b;
480
    f3m_cubic
481
        ins1 (in, a), // a == in^3
482
        ins2 (a, b);  // b == a^3 == in^9
483
    always @ (posedge clk)
484
        out <= b;
485
endmodule
486
 
487
// inversion in GF(3^m). C = A^(-1)
488 7 homer.xing
module f3m_inv(clk, reset, A, C, done);
489 2 homer.xing
        input [`WIDTH:0] A;
490
        input clk;
491
        input reset;
492
        output reg [`WIDTH:0] C;
493 7 homer.xing
    output reg done;
494 2 homer.xing
 
495
        reg [`WIDTH+2:0] S, R, U, V, d, i;
496
        wire [1:0] q;
497
        wire [`WIDTH+2:0] S1, S2,
498
                          R1,
499
                          U1, U2, U3,
500
                          V1, V2,
501
                          d1, d2,
502
                      i1;
503 7 homer.xing
        wire don;
504 2 homer.xing
 
505
        assign d1 = {d[`WIDTH+1:0], 1'b1}; // d1 == d+1
506
        assign d2 = {1'b0, d[`WIDTH+2:1]}; // d2 == d-1
507
    assign i1 = {1'b0, i[`WIDTH+2:1]}; // i1 == i-1
508 7 homer.xing
        assign don = (i[2:1] == 2'b01);
509 2 homer.xing
 
510 7 homer.xing
        always @ (posedge clk)
511
        if (reset)
512
            done <= 0;
513
            else if (don)
514 2 homer.xing
          begin
515 7 homer.xing
                done <= 1; C <= U2[`WIDTH:0];
516 2 homer.xing
          end
517
 
518
        f3_mult
519
            q1(S[`MOST], R[`MOST], q); // q = s_m / r_m
520
        func1
521
            ins1(S, R, q, S1), // S1 = S - q*R
522
            ins2(V, U, q, V1); // V1 = V - q*U
523
        func2
524
            ins3(S1, S2), // S2 = x*S1 = x*(S-q*R)
525
            ins4(R, R1); // R1 = x*R
526
        func3
527
            ins5(U, U1), // U1 = x*U mod p
528
            ins6(V1, V2); // V2 = x*V1 mod p = x*(V-qU) mod p
529
    func4
530
        ins7(U, R[`MOST], U2); // U2 = U/r_m
531
    func5
532
        ins8(U, U3); // U3 = (U/x) mod p
533
 
534
    always @ (posedge clk)
535
        if (reset)
536
            i <= ~0;
537
        else
538
            i <= i1;
539
 
540
    always @ (posedge clk)
541
        if (reset)
542
          begin
543
            S<=`PX; R<=A; U<=1; V<=0; d<=0;
544
          end
545
        else if (R[`MOST] == 2'b0)
546
          begin
547
            R<=R1; U<=U1; d<=d1;
548
          end
549
        else if (d[0] == 1'b0) // d == 0
550
          begin
551
            R<=S2; S<=R; U<=V2; V<=U; d<=d1;
552
          end
553
        else // d != 0
554
          begin
555
            S<=S2; V<=V1; U<=U3; d<=d2;
556
          end
557
endmodule
558
 
559 3 homer.xing
// put func1~5 here for breaking circular dependency in "f3m", "fun"
560
 
561
// out = S - q*R
562
module func1(S, R, q, out);
563
    input [`WIDTH+2:0] S, R;
564
    input [1:0] q;
565
    output [`WIDTH+2:0] out;
566
    wire [`WIDTH+2:0] t;
567
    func4 f(R, q, t); // t == q*R
568
    genvar i;
569
    generate for(i=0; i<=`WIDTH+2; i=i+2) begin: label
570
        f3_sub s1(S[i+1:i], t[i+1:i], out[i+1:i]); // out == S - t
571
    end endgenerate
572
endmodule
573
 
574
// out = x*A
575
module func2(A, out);
576
    input [`WIDTH+2:0] A;
577
    output [`WIDTH+2:0] out;
578
    assign out = {A[`WIDTH:0], 2'd0};
579
endmodule
580
 
581
// C = (x*B mod p(x))
582
module func3(B, C);
583
    input [`WIDTH+2:0] B;
584
    output [`WIDTH+2:0] C;
585
    wire [`WIDTH+2:0] A;
586
    assign A = {B[`WIDTH:0], 2'd0}; // A == B*x
587
    wire [1:0] w0;
588
    f3_mult m0 (A[195:194], 2'd2, w0);
589
    f3_sub s0 (A[1:0], w0, C[1:0]);
590
    assign C[23:2] = A[23:2];
591
    wire [1:0] w12;
592
    f3_mult m12 (A[195:194], 2'd1, w12);
593
    f3_sub s12 (A[25:24], w12, C[25:24]);
594
    assign C[193:26] = A[193:26];
595
    assign C[195:194] = 0;
596
endmodule
597
 
598
// C = a * A; A,C \in GF(3^m); a \in GF(3)
599
module func4(A, aa, C);
600
    input [`WIDTH+2:0] A;
601
    input [1:0] aa;
602
    output [`WIDTH+2:0] C;
603
    genvar i;
604
    generate
605
      for(i=0; i<=`WIDTH+2; i=i+2)
606
      begin: label
607
        f3_mult m(A[i+1:i], aa, C[i+1:i]);
608
      end
609
    endgenerate
610
endmodule
611
 
612
// C = (A/x) mod p, \in GF(3^m)
613
module func5(A, C);
614
    input [`WIDTH+2:0] A;
615
    output [`WIDTH+2:0] C;
616
    assign C[195:194] = 0;
617
    assign C[193:192] = A[1:0];
618
    assign C[191:24] = A[193:26];
619
    f3_add a11 (A[25:24], A[1:0], C[23:22]);
620
    assign C[21:0] = A[23:2];
621
endmodule

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