OpenCores

Subversion Repositories pairing

[/] [pairing/] [trunk/] [rtl/] [f3m.v] - Blame information for rev 28

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 homer.xing
/*
2
    Copyright 2011, City University of Hong Kong
3
    Author is Homer (Dongsheng) Xing.
4
 
5
    This file is part of Tate Bilinear Pairing Core.
6
 
7
    Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
8
    it under the terms of the GNU Lesser General Public License as published by
9
    the Free Software Foundation, either version 3 of the License, or
10
    (at your option) any later version.
11
 
12
    Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
13
    but WITHOUT ANY WARRANTY; without even the implied warranty of
14
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
    GNU Lesser General Public License for more details.
16
 
17
    You should have received a copy of the GNU General Public License
18
    along with Foobar.  If not, see http://www.gnu.org/licenses/lgpl.txt
19
*/
20
 
21 2 homer.xing
`include "inc.v"
22
`define MOST 2*`M+1:2*`M
23
 
24 3 homer.xing
// out = (v1 & l1) | (v2 & l2) | (v3 & l3)
25
module f3m_mux3(v1, l1, v2, l2, v3, l3, out);
26
    input [`WIDTH:0] v1, v2, v3;
27
    input l1, l2, l3;
28
    output [`WIDTH:0] out;
29
    genvar i;
30
    generate
31
        for(i=0;i<=`WIDTH;i=i+1)
32
          begin : label
33
            assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
34
          end
35
    endgenerate
36
endmodule
37
 
38
// out = (v0 & l0) | (v1 & l1) | (v2 & l2) | ... | (v5 & l5)
39
module f3m_mux6(v0, v1, v2, v3, v4, v5, l0, l1, l2, l3, l4, l5, out);
40
    input l0, l1, l2, l3, l4, l5;
41
    input [`WIDTH:0] v0, v1, v2, v3, v4, v5;
42 17 homer.xing
    output [`WIDTH:0] out;
43
    genvar i;
44
    generate
45
        for(i=0;i<=`WIDTH;i=i+1)
46
          begin : label
47
            assign out[i] = (v0[i]&l0)|(v1[i]&l1)|(v2[i]&l2)|(v3[i]&l3)|(v4[i]&l4)|(v5[i]&l5);
48
          end
49
    endgenerate
50 3 homer.xing
endmodule
51
 
52 2 homer.xing
// f3m_add: C = A + B, in field F_{3^M}
53
module f3m_add(A, B, C);
54
    input [`WIDTH : 0] A, B;
55
    output [`WIDTH : 0] C;
56
    genvar i;
57
    generate
58
        for(i=0; i<`M; i=i+1) begin: aa
59
            f3_add aa(A[(2*i+1) : 2*i], B[(2*i+1) : 2*i], C[(2*i+1) : 2*i]);
60
        end
61
    endgenerate
62
endmodule
63
 
64 3 homer.xing
// f3m_add3: c == a0+a1+a2, in field GF(3^M)
65
module f3m_add3(a0, a1, a2, c);
66
    input [`WIDTH:0] a0,a1,a2;
67
    output [`WIDTH:0] c;
68
    wire [`WIDTH:0] v;
69
    f3m_add
70
        ins1 (a0,a1,v), // v == a0+a1
71
        ins2 (v,a2,c);  // c == v+a2 == a0+a1+a2
72
endmodule
73
 
74
// f3m_add4: c == a0+a1+a2+a3, in field GF(3^M)
75
module f3m_add4(a0, a1, a2, a3, c);
76
    input [`WIDTH:0] a0,a1,a2,a3;
77
    output [`WIDTH:0] c;
78
    wire [`WIDTH:0] v1,v2;
79
    f3m_add
80
        ins1 (a0,a1,v1), // v1 == a0+a1
81
        ins2 (a2,a3,v2), // v2 == a2+a3
82
        ins3 (v1,v2,c);  // c == v1+v2 == a0+a1+a2+a3
83
endmodule
84
 
85 2 homer.xing
// f3m_neg: c == -a in GF(3^M)
86
module f3m_neg(a, c);
87
    input [`WIDTH:0] a;
88
    output [`WIDTH:0] c;
89
    genvar i;
90
    generate
91
        for(i=0;i<=`WIDTH;i=i+2)
92
          begin:label
93
            assign c[i+1:i] = {a[i],a[i+1]};
94
          end
95
    endgenerate
96
endmodule
97
 
98
// f3m_sub: C = A - B, in field F_{3^M}
99
module f3m_sub(A, B, C);
100
    input [`WIDTH : 0] A, B;
101
    output [`WIDTH : 0] C;
102
    genvar i;
103
    generate
104
        for(i=0; i<`M; i=i+1) begin: aa
105
            f3_sub aa(A[(2*i+1) : 2*i], B[(2*i+1) : 2*i], C[(2*i+1) : 2*i]);
106
        end
107
    endgenerate
108
endmodule
109
 
110
// f3m_mult: C = A * B, in field GF(3^M)
111
module f3m_mult(clk, reset, A, B, C, done);
112
    input [`WIDTH : 0] A, B;
113
    input clk;
114
    input reset;
115
    output reg [`WIDTH : 0] C;
116
    output reg done;
117
    reg [`WIDTH : 0] x, y, z;
118 11 homer.xing
    wire [`WIDTH : 0] z1, z2, z3, z4;
119
    reg [`M/3+1 : 0] i;
120 2 homer.xing
    wire done1;
121
    wire [1:0] dummy;
122
 
123 11 homer.xing
    func8
124
        ins1 (x, y[5:0], z1); // z1 == A * (B[2]*x^2 + B[1]*x + B[0])
125 2 homer.xing
    f3m_add
126 11 homer.xing
        ins2 (z1, z, z2); // z2 == z1 + z == A * (B[2]*x^2 + B[1]*x + B[0]) + z
127
    assign z4 = y >> 6; // z4 == y >> 6
128
    func7
129
        ins3 (x, z3); // z3 == X*(x^3) mod p(x)
130 8 homer.xing
    assign done1 = i[0];
131 2 homer.xing
 
132
    always @ (posedge clk)
133
        if (done1)
134
            C <= z;
135
 
136
    always @ (posedge clk)
137
        if (reset)
138
            done <= 0;
139
        else if (done1)
140
            done <= 1;
141
 
142
    always @ (posedge clk)
143
      begin
144
        if (reset)
145
          begin
146 11 homer.xing
            x <= A; y <= B; z <= 0; i <= {1'b1,{(`M/3+1){1'b0}}};
147 2 homer.xing
          end
148
        else
149
          begin
150 8 homer.xing
            x <= z3[`WIDTH:0]; y <= z4; z <= z2; i <= i >> 1;
151 2 homer.xing
          end
152
      end
153
endmodule
154
 
155 7 homer.xing
// c0 == a0*b0; c1 == a1*b1; c2 == a2*b2; all in GF(3^M)
156
module f3m_mult3(clk, reset,
157
                 a0, b0, c0,
158
                 a1, b1, c1,
159
                 a2, b2, c2,
160
                 done);
161
    input clk, reset;
162
    input [`WIDTH:0] a0, b0, a1, b1, a2, b2;
163
    output reg [`WIDTH:0] c0, c1, c2;
164
    output reg done;
165
    reg [3:0] K;
166
    reg mult_reset, delay1, delay2;
167
    wire e1, e2, e3, mult_done, delay3, rst;
168
    wire [`WIDTH:0] in1, in2, o;
169
 
170
    assign rst = delay2;
171
    assign {e1,e2,e3} = K[3:1];
172
 
173
    f3m_mux3
174
        ins9 (a0, e1, a1, e2, a2, e3, in1),
175
        ins10 (b0, e1, b1, e2, b2, e3, in2);
176
    f3m_mult
177
        ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2 in GF(3^m)
178
    func6
179 8 homer.xing
        ins12 (clk, reset, mult_done, delay3);
180 7 homer.xing
 
181
    always @ (posedge clk)
182
      begin
183
        if (e1) c0 <= o;
184
        if (e2) c1 <= o;
185
        if (e3) c2 <= o;
186
      end
187
 
188
    always @ (posedge clk)
189
        if (reset) K <= 4'b1000;
190 8 homer.xing
        else if (delay3 | K[0]) K <= {1'b0,K[3:1]};
191 7 homer.xing
 
192
    always @ (posedge clk)
193
      begin
194
        if (rst) mult_reset <= 1;
195
        else if (mult_done) mult_reset <= 1;
196
        else mult_reset <= 0;
197
      end
198
 
199
    always @ (posedge clk)
200
        if (reset)     done <= 0;
201
        else if (K[0]) done <= 1;
202
 
203
    always @ (posedge clk)
204
      begin
205
        delay2 <= delay1; delay1 <= reset;
206
      end
207
endmodule
208
 
209 2 homer.xing
/* out == in^3 mod p(x) */
210
/* p(x) == x^97 + x^12 + 2 */
211 28 homer.xing
module f3m_cubic(input wire [193:0] in, output wire [193:0] out);
212 2 homer.xing
wire [1:0] w0; f3_add a0(in[131:130], in[139:138], w0);
213
wire [1:0] w1; f3_add a1(in[133:132], in[141:140], w1);
214
wire [1:0] w2; f3_add a2(in[135:134], in[143:142], w2);
215
wire [1:0] w3; f3_add a3(in[137:136], in[145:144], w3);
216
wire [1:0] w4; f3_add a4(in[147:146], in[155:154], w4);
217
wire [1:0] w5; f3_add a5(in[149:148], in[157:156], w5);
218
wire [1:0] w6; f3_add a6(in[151:150], in[159:158], w6);
219
wire [1:0] w7; f3_add a7(in[153:152], in[161:160], w7);
220
wire [1:0] w8; f3_add a8(in[163:162], in[171:170], w8);
221
wire [1:0] w9; f3_add a9(in[165:164], in[173:172], w9);
222
wire [1:0] w10; f3_add a10(in[167:166], in[175:174], w10);
223
wire [1:0] w11; f3_add a11(in[169:168], in[177:176], w11);
224
wire [1:0] w12; f3_add a12(in[179:178], in[187:186], w12);
225
wire [1:0] w13; f3_add a13(in[181:180], in[189:188], w13);
226
wire [1:0] w14; f3_add a14(in[183:182], in[191:190], w14);
227
wire [1:0] w15; f3_add a15(in[185:184], in[193:192], w15);
228
wire [1:0] w16;
229
f3_add a16(in[1:0], w12, w16);
230
assign out[1:0] = w16;
231
wire [1:0] w17;
232
f3_add a17({in[122],in[123]}, in[131:130], w17);
233
assign out[3:2] = w17;
234
assign out[5:4] = in[67:66];
235
wire [1:0] w18;
236
f3_add a18(in[3:2], w13, w18);
237
assign out[7:6] = w18;
238
wire [1:0] w19;
239
f3_add a19({in[124],in[125]}, in[133:132], w19);
240
assign out[9:8] = w19;
241
assign out[11:10] = in[69:68];
242
wire [1:0] w20;
243
f3_add a20(in[5:4], w14, w20);
244
assign out[13:12] = w20;
245
wire [1:0] w21;
246
f3_add a21({in[126],in[127]}, in[135:134], w21);
247
assign out[15:14] = w21;
248
assign out[17:16] = in[71:70];
249
wire [1:0] w22;
250
f3_add a22(in[7:6], w15, w22);
251
assign out[19:18] = w22;
252
wire [1:0] w23;
253
f3_add a23({in[128],in[129]}, in[137:136], w23);
254
assign out[21:20] = w23;
255
assign out[23:22] = in[73:72];
256
wire [1:0] w24;
257
f3_add a24(in[9:8], {in[178],in[179]}, w24);
258
assign out[25:24] = w24;
259
wire [1:0] w25;
260
f3_add a25(in[123:122], w0, w25);
261
assign out[27:26] = w25;
262
wire [1:0] w26;
263
f3_add a26({in[66],in[67]}, in[75:74], w26);
264
assign out[29:28] = w26;
265
wire [1:0] w27;
266
f3_add a27(in[11:10], {in[180],in[181]}, w27);
267
assign out[31:30] = w27;
268
wire [1:0] w28;
269
f3_add a28(in[125:124], w1, w28);
270
assign out[33:32] = w28;
271
wire [1:0] w29;
272
f3_add a29({in[68],in[69]}, in[77:76], w29);
273
assign out[35:34] = w29;
274
wire [1:0] w30;
275
f3_add a30(in[13:12], {in[182],in[183]}, w30);
276
assign out[37:36] = w30;
277
wire [1:0] w31;
278
f3_add a31(in[127:126], w2, w31);
279
assign out[39:38] = w31;
280
wire [1:0] w32;
281
f3_add a32({in[70],in[71]}, in[79:78], w32);
282
assign out[41:40] = w32;
283
wire [1:0] w33;
284
f3_add a33(in[15:14], {in[184],in[185]}, w33);
285
assign out[43:42] = w33;
286
wire [1:0] w34;
287
f3_add a34(in[129:128], w3, w34);
288
assign out[45:44] = w34;
289
wire [1:0] w35;
290
f3_add a35({in[72],in[73]}, in[81:80], w35);
291
assign out[47:46] = w35;
292
wire [1:0] w36;
293
f3_add a36(in[17:16], {in[186],in[187]}, w36);
294
assign out[49:48] = w36;
295
wire [1:0] w37;
296
f3_add a37(in[147:146], w0, w37);
297
assign out[51:50] = w37;
298
wire [1:0] w38;
299
f3_add a38({in[74],in[75]}, in[83:82], w38);
300
assign out[53:52] = w38;
301
wire [1:0] w39;
302
f3_add a39(in[19:18], {in[188],in[189]}, w39);
303
assign out[55:54] = w39;
304
wire [1:0] w40;
305
f3_add a40(in[149:148], w1, w40);
306
assign out[57:56] = w40;
307
wire [1:0] w41;
308
f3_add a41({in[76],in[77]}, in[85:84], w41);
309
assign out[59:58] = w41;
310
wire [1:0] w42;
311
f3_add a42(in[21:20], {in[190],in[191]}, w42);
312
assign out[61:60] = w42;
313
wire [1:0] w43;
314
f3_add a43(in[151:150], w2, w43);
315
assign out[63:62] = w43;
316
wire [1:0] w44;
317
f3_add a44({in[78],in[79]}, in[87:86], w44);
318
assign out[65:64] = w44;
319
wire [1:0] w45;
320
f3_add a45(in[23:22], {in[192],in[193]}, w45);
321
assign out[67:66] = w45;
322
wire [1:0] w46;
323
f3_add a46(in[153:152], w3, w46);
324
assign out[69:68] = w46;
325
wire [1:0] w47;
326
f3_add a47({in[80],in[81]}, in[89:88], w47);
327
assign out[71:70] = w47;
328
assign out[73:72] = in[25:24];
329
wire [1:0] w48;
330
f3_add a48(in[139:138], w4, w48);
331
assign out[75:74] = w48;
332
wire [1:0] w49;
333
f3_add a49({in[82],in[83]}, in[91:90], w49);
334
assign out[77:76] = w49;
335
assign out[79:78] = in[27:26];
336
wire [1:0] w50;
337
f3_add a50(in[141:140], w5, w50);
338
assign out[81:80] = w50;
339
wire [1:0] w51;
340
f3_add a51({in[84],in[85]}, in[93:92], w51);
341
assign out[83:82] = w51;
342
assign out[85:84] = in[29:28];
343
wire [1:0] w52;
344
f3_add a52(in[143:142], w6, w52);
345
assign out[87:86] = w52;
346
wire [1:0] w53;
347
f3_add a53({in[86],in[87]}, in[95:94], w53);
348
assign out[89:88] = w53;
349
assign out[91:90] = in[31:30];
350
wire [1:0] w54;
351
f3_add a54(in[145:144], w7, w54);
352
assign out[93:92] = w54;
353
wire [1:0] w55;
354
f3_add a55({in[88],in[89]}, in[97:96], w55);
355
assign out[95:94] = w55;
356
assign out[97:96] = in[33:32];
357
wire [1:0] w56;
358
f3_add a56(in[163:162], w4, w56);
359
assign out[99:98] = w56;
360
wire [1:0] w57;
361
f3_add a57({in[90],in[91]}, in[99:98], w57);
362
assign out[101:100] = w57;
363
assign out[103:102] = in[35:34];
364
wire [1:0] w58;
365
f3_add a58(in[165:164], w5, w58);
366
assign out[105:104] = w58;
367
wire [1:0] w59;
368
f3_add a59({in[92],in[93]}, in[101:100], w59);
369
assign out[107:106] = w59;
370
assign out[109:108] = in[37:36];
371
wire [1:0] w60;
372
f3_add a60(in[167:166], w6, w60);
373
assign out[111:110] = w60;
374
wire [1:0] w61;
375
f3_add a61({in[94],in[95]}, in[103:102], w61);
376
assign out[113:112] = w61;
377
assign out[115:114] = in[39:38];
378
wire [1:0] w62;
379
f3_add a62(in[169:168], w7, w62);
380
assign out[117:116] = w62;
381
wire [1:0] w63;
382
f3_add a63({in[96],in[97]}, in[105:104], w63);
383
assign out[119:118] = w63;
384
assign out[121:120] = in[41:40];
385
wire [1:0] w64;
386
f3_add a64(in[155:154], w8, w64);
387
assign out[123:122] = w64;
388
wire [1:0] w65;
389
f3_add a65({in[98],in[99]}, in[107:106], w65);
390
assign out[125:124] = w65;
391
assign out[127:126] = in[43:42];
392
wire [1:0] w66;
393
f3_add a66(in[157:156], w9, w66);
394
assign out[129:128] = w66;
395
wire [1:0] w67;
396
f3_add a67({in[100],in[101]}, in[109:108], w67);
397
assign out[131:130] = w67;
398
assign out[133:132] = in[45:44];
399
wire [1:0] w68;
400
f3_add a68(in[159:158], w10, w68);
401
assign out[135:134] = w68;
402
wire [1:0] w69;
403
f3_add a69({in[102],in[103]}, in[111:110], w69);
404
assign out[137:136] = w69;
405
assign out[139:138] = in[47:46];
406
wire [1:0] w70;
407
f3_add a70(in[161:160], w11, w70);
408
assign out[141:140] = w70;
409
wire [1:0] w71;
410
f3_add a71({in[104],in[105]}, in[113:112], w71);
411
assign out[143:142] = w71;
412
assign out[145:144] = in[49:48];
413
wire [1:0] w72;
414
f3_add a72(in[179:178], w8, w72);
415
assign out[147:146] = w72;
416
wire [1:0] w73;
417
f3_add a73({in[106],in[107]}, in[115:114], w73);
418
assign out[149:148] = w73;
419
assign out[151:150] = in[51:50];
420
wire [1:0] w74;
421
f3_add a74(in[181:180], w9, w74);
422
assign out[153:152] = w74;
423
wire [1:0] w75;
424
f3_add a75({in[108],in[109]}, in[117:116], w75);
425
assign out[155:154] = w75;
426
assign out[157:156] = in[53:52];
427
wire [1:0] w76;
428
f3_add a76(in[183:182], w10, w76);
429
assign out[159:158] = w76;
430
wire [1:0] w77;
431
f3_add a77({in[110],in[111]}, in[119:118], w77);
432
assign out[161:160] = w77;
433
assign out[163:162] = in[55:54];
434
wire [1:0] w78;
435
f3_add a78(in[185:184], w11, w78);
436
assign out[165:164] = w78;
437
wire [1:0] w79;
438
f3_add a79({in[112],in[113]}, in[121:120], w79);
439
assign out[167:166] = w79;
440
assign out[169:168] = in[57:56];
441
wire [1:0] w80;
442
f3_add a80(in[171:170], w12, w80);
443
assign out[171:170] = w80;
444
wire [1:0] w81;
445
f3_add a81({in[114],in[115]}, in[123:122], w81);
446
assign out[173:172] = w81;
447
assign out[175:174] = in[59:58];
448
wire [1:0] w82;
449
f3_add a82(in[173:172], w13, w82);
450
assign out[177:176] = w82;
451
wire [1:0] w83;
452
f3_add a83({in[116],in[117]}, in[125:124], w83);
453
assign out[179:178] = w83;
454
assign out[181:180] = in[61:60];
455
wire [1:0] w84;
456
f3_add a84(in[175:174], w14, w84);
457
assign out[183:182] = w84;
458
wire [1:0] w85;
459
f3_add a85({in[118],in[119]}, in[127:126], w85);
460
assign out[185:184] = w85;
461
assign out[187:186] = in[63:62];
462
wire [1:0] w86;
463
f3_add a86(in[177:176], w15, w86);
464
assign out[189:188] = w86;
465
wire [1:0] w87;
466
f3_add a87({in[120],in[121]}, in[129:128], w87);
467
assign out[191:190] = w87;
468
assign out[193:192] = in[65:64];
469
endmodule
470
 
471
/* nine square in GF(3^m), out = in^9 mod p(x) */
472
/* p(x) == x^97 + x^12 + 2 */
473
module f3m_nine(clk, in, out);
474
    input clk;
475
    input [`WIDTH:0] in;
476
    output reg [`WIDTH:0] out;
477
    wire [`WIDTH:0] a,b;
478
    f3m_cubic
479
        ins1 (in, a), // a == in^3
480
        ins2 (a, b);  // b == a^3 == in^9
481
    always @ (posedge clk)
482
        out <= b;
483
endmodule
484
 
485
// inversion in GF(3^m). C = A^(-1)
486 7 homer.xing
module f3m_inv(clk, reset, A, C, done);
487 22 homer.xing
    input [`WIDTH:0] A;
488
    input clk;
489
    input reset;
490
    output reg [`WIDTH:0] C;
491 7 homer.xing
    output reg done;
492 22 homer.xing
 
493
    reg [`WIDTH+2:0] S, R, U, V, d;
494
    reg [2*`M:0] i;
495
    wire [1:0] q;
496
    wire [`WIDTH+2:0] S1, S2,
497
                      R1,
498
                      U1, U2, U3,
499
                      V1, V2,
500
                      d1, d2;
501
    wire don;
502 2 homer.xing
 
503 22 homer.xing
    assign d1 = {d[`WIDTH+1:0], 1'b1}; // d1 == d+1
504
    assign d2 = {1'b0, d[`WIDTH+2:1]}; // d2 == d-1
505
    assign don = i[0];
506
 
507
    f3_mult
508
        q1(S[`MOST], R[`MOST], q); // q = s_m / r_m
509
    func1
510
        ins1(S, R, q, S1), // S1 = S - q*R
511
        ins2(V, U, q, V1); // V1 = V - q*U
512
    func2
513
        ins3(S1, S2), // S2 = x*S1 = x*(S-q*R)
514
        ins4(R, R1); // R1 = x*R
515
    func3
516
        ins5(U, U1), // U1 = x*U mod p
517
        ins6(V1, V2); // V2 = x*V1 mod p = x*(V-qU) mod p
518 2 homer.xing
    func4
519
        ins7(U, R[`MOST], U2); // U2 = U/r_m
520
    func5
521
        ins8(U, U3); // U3 = (U/x) mod p
522
 
523 22 homer.xing
    always @ (posedge clk)
524 8 homer.xing
        if (reset)
525
            done <= 0;
526 22 homer.xing
        else if (don)
527 8 homer.xing
          begin
528 22 homer.xing
            done <= 1; C <= U2[`WIDTH:0];
529 8 homer.xing
          end
530
 
531 2 homer.xing
    always @ (posedge clk)
532
        if (reset)
533 8 homer.xing
            i <= {1'b1, {(2*`M){1'b0}}};
534 2 homer.xing
        else
535 8 homer.xing
            i <= i >> 1;
536 2 homer.xing
 
537
    always @ (posedge clk)
538
        if (reset)
539
          begin
540
            S<=`PX; R<=A; U<=1; V<=0; d<=0;
541
          end
542
        else if (R[`MOST] == 2'b0)
543
          begin
544
            R<=R1; U<=U1; d<=d1;
545
          end
546
        else if (d[0] == 1'b0) // d == 0
547
          begin
548
            R<=S2; S<=R; U<=V2; V<=U; d<=d1;
549
          end
550
        else // d != 0
551
          begin
552
            S<=S2; V<=V1; U<=U3; d<=d2;
553
          end
554
endmodule
555
 
556 3 homer.xing
// put func1~5 here for breaking circular dependency in "f3m", "fun"
557
 
558
// out = S - q*R
559
module func1(S, R, q, out);
560
    input [`WIDTH+2:0] S, R;
561
    input [1:0] q;
562
    output [`WIDTH+2:0] out;
563
    wire [`WIDTH+2:0] t;
564
    func4 f(R, q, t); // t == q*R
565
    genvar i;
566
    generate for(i=0; i<=`WIDTH+2; i=i+2) begin: label
567
        f3_sub s1(S[i+1:i], t[i+1:i], out[i+1:i]); // out == S - t
568
    end endgenerate
569
endmodule
570
 
571
// out = x*A
572
module func2(A, out);
573
    input [`WIDTH+2:0] A;
574
    output [`WIDTH+2:0] out;
575
    assign out = {A[`WIDTH:0], 2'd0};
576
endmodule
577
 
578
// C = (x*B mod p(x))
579
module func3(B, C);
580
    input [`WIDTH+2:0] B;
581
    output [`WIDTH+2:0] C;
582
    wire [`WIDTH+2:0] A;
583
    assign A = {B[`WIDTH:0], 2'd0}; // A == B*x
584
    wire [1:0] w0;
585
    f3_mult m0 (A[195:194], 2'd2, w0);
586
    f3_sub s0 (A[1:0], w0, C[1:0]);
587
    assign C[23:2] = A[23:2];
588
    wire [1:0] w12;
589
    f3_mult m12 (A[195:194], 2'd1, w12);
590
    f3_sub s12 (A[25:24], w12, C[25:24]);
591
    assign C[193:26] = A[193:26];
592
    assign C[195:194] = 0;
593
endmodule
594
 
595
// C = a * A; A,C \in GF(3^m); a \in GF(3)
596
module func4(A, aa, C);
597
    input [`WIDTH+2:0] A;
598
    input [1:0] aa;
599
    output [`WIDTH+2:0] C;
600
    genvar i;
601
    generate
602
      for(i=0; i<=`WIDTH+2; i=i+2)
603
      begin: label
604
        f3_mult m(A[i+1:i], aa, C[i+1:i]);
605
      end
606
    endgenerate
607
endmodule
608
 
609
// C = (A/x) mod p, \in GF(3^m)
610
module func5(A, C);
611
    input [`WIDTH+2:0] A;
612
    output [`WIDTH+2:0] C;
613
    assign C[195:194] = 0;
614
    assign C[193:192] = A[1:0];
615
    assign C[191:24] = A[193:26];
616
    f3_add a11 (A[25:24], A[1:0], C[23:22]);
617
    assign C[21:0] = A[23:2];
618
endmodule
619 11 homer.xing
 
620
/* $C=A*(x^3) mod p(x)$ */
621
/* p(x) == x^97 + x^12 + 2 */
622 28 homer.xing
module func7(input wire [193:0] in, output wire [193:0] out);
623 11 homer.xing
    assign out[5:0] = in[193:188];
624
    assign out[23:6] = in[17:0];
625
    wire [1:0] w0;
626
    f3_add a0(in[19:18], {in[188],in[189]}, w0);
627
    assign out[25:24] = w0;
628
    wire [1:0] w1;
629
    f3_add a1(in[21:20], {in[190],in[191]}, w1);
630
    assign out[27:26] = w1;
631
    wire [1:0] w2;
632
    f3_add a2(in[23:22], {in[192],in[193]}, w2);
633
    assign out[29:28] = w2;
634
    assign out[193:30] = in[187:24];
635
endmodule
636
 
637
/* c = (b_2 x^2 + b_1 x + b_0)*A mod p(x) */
638
module func8 (a, b, c);
639
input [193:0] a;
640
input [5:0] b;
641
output [193:0] c;
642
wire [1:0] w1; f3_mult m2 (a[1:0], b[1:0], w1);
643
wire [1:0] w3; f3_mult m4 (a[191:190], b[5:4], w3);
644
wire [1:0] w5; f3_mult m6 (a[193:192], b[3:2], w5);
645
wire [1:0] w7; f3_add a8 (w1, w3, w7);
646
wire [1:0] w9; f3_add a10 (w7, w5, w9);
647
assign c[1:0] = w9;
648
wire [1:0] w11; f3_mult m12 (a[1:0], b[3:2], w11);
649
wire [1:0] w13; f3_mult m14 (a[193:192], b[5:4], w13);
650
wire [1:0] w15; f3_mult m16 (a[3:2], b[1:0], w15);
651
wire [1:0] w17; f3_add a18 (w11, w13, w17);
652
wire [1:0] w19; f3_add a20 (w17, w15, w19);
653
assign c[3:2] = w19;
654
wire [1:0] w21; f3_mult m22 (a[5:4], b[1:0], w21);
655
wire [1:0] w23; f3_mult m24 (a[1:0], b[5:4], w23);
656
wire [1:0] w25; f3_mult m26 (a[3:2], b[3:2], w25);
657
wire [1:0] w27; f3_add a28 (w21, w23, w27);
658
wire [1:0] w29; f3_add a30 (w27, w25, w29);
659
assign c[5:4] = w29;
660
wire [1:0] w31; f3_mult m32 (a[7:6], b[1:0], w31);
661
wire [1:0] w33; f3_mult m34 (a[3:2], b[5:4], w33);
662
wire [1:0] w35; f3_mult m36 (a[5:4], b[3:2], w35);
663
wire [1:0] w37; f3_add a38 (w31, w33, w37);
664
wire [1:0] w39; f3_add a40 (w37, w35, w39);
665
assign c[7:6] = w39;
666
wire [1:0] w41; f3_mult m42 (a[7:6], b[3:2], w41);
667
wire [1:0] w43; f3_mult m44 (a[9:8], b[1:0], w43);
668
wire [1:0] w45; f3_mult m46 (a[5:4], b[5:4], w45);
669
wire [1:0] w47; f3_add a48 (w41, w43, w47);
670
wire [1:0] w49; f3_add a50 (w47, w45, w49);
671
assign c[9:8] = w49;
672
wire [1:0] w51; f3_mult m52 (a[11:10], b[1:0], w51);
673
wire [1:0] w53; f3_mult m54 (a[7:6], b[5:4], w53);
674
wire [1:0] w55; f3_mult m56 (a[9:8], b[3:2], w55);
675
wire [1:0] w57; f3_add a58 (w51, w53, w57);
676
wire [1:0] w59; f3_add a60 (w57, w55, w59);
677
assign c[11:10] = w59;
678
wire [1:0] w61; f3_mult m62 (a[13:12], b[1:0], w61);
679
wire [1:0] w63; f3_mult m64 (a[11:10], b[3:2], w63);
680
wire [1:0] w65; f3_mult m66 (a[9:8], b[5:4], w65);
681
wire [1:0] w67; f3_add a68 (w61, w63, w67);
682
wire [1:0] w69; f3_add a70 (w67, w65, w69);
683
assign c[13:12] = w69;
684
wire [1:0] w71; f3_mult m72 (a[13:12], b[3:2], w71);
685
wire [1:0] w73; f3_mult m74 (a[15:14], b[1:0], w73);
686
wire [1:0] w75; f3_mult m76 (a[11:10], b[5:4], w75);
687
wire [1:0] w77; f3_add a78 (w71, w73, w77);
688
wire [1:0] w79; f3_add a80 (w77, w75, w79);
689
assign c[15:14] = w79;
690
wire [1:0] w81; f3_mult m82 (a[13:12], b[5:4], w81);
691
wire [1:0] w83; f3_mult m84 (a[15:14], b[3:2], w83);
692
wire [1:0] w85; f3_mult m86 (a[17:16], b[1:0], w85);
693
wire [1:0] w87; f3_add a88 (w81, w83, w87);
694
wire [1:0] w89; f3_add a90 (w87, w85, w89);
695
assign c[17:16] = w89;
696
wire [1:0] w91; f3_mult m92 (a[15:14], b[5:4], w91);
697
wire [1:0] w93; f3_mult m94 (a[19:18], b[1:0], w93);
698
wire [1:0] w95; f3_mult m96 (a[17:16], b[3:2], w95);
699
wire [1:0] w97; f3_add a98 (w91, w93, w97);
700
wire [1:0] w99; f3_add a100 (w97, w95, w99);
701
assign c[19:18] = w99;
702
wire [1:0] w101; f3_mult m102 (a[21:20], b[1:0], w101);
703
wire [1:0] w103; f3_mult m104 (a[17:16], b[5:4], w103);
704
wire [1:0] w105; f3_mult m106 (a[19:18], b[3:2], w105);
705
wire [1:0] w107; f3_add a108 (w101, w103, w107);
706
wire [1:0] w109; f3_add a110 (w107, w105, w109);
707
assign c[21:20] = w109;
708
wire [1:0] w111; f3_mult m112 (a[23:22], b[1:0], w111);
709
wire [1:0] w113; f3_mult m114 (a[19:18], b[5:4], w113);
710
wire [1:0] w115; f3_mult m116 (a[21:20], b[3:2], w115);
711
wire [1:0] w117; f3_add a118 (w111, w113, w117);
712
wire [1:0] w119; f3_add a120 (w117, w115, w119);
713
assign c[23:22] = w119;
714
wire [1:0] w121; f3_mult m122 (a[23:22], b[3:2], w121);
715
wire [1:0] w123; f3_mult m124 (a[25:24], b[1:0], w123);
716
wire [1:0] w125; f3_mult m126 (a[21:20], b[5:4], w125);
717
wire [1:0] w127; f3_add a128 (w121, w123, w127);
718
wire [1:0] w129; f3_add a130 (w127, w125, w129);
719
wire [1:0] w131; f3_add a132 (w129, {w5[0], w5[1]}, w131);
720
wire [1:0] w133; f3_add a134 (w131, {w3[0], w3[1]}, w133);
721
assign c[25:24] = w133;
722
wire [1:0] w135; f3_mult m136 (a[27:26], b[1:0], w135);
723
wire [1:0] w137; f3_mult m138 (a[23:22], b[5:4], w137);
724
wire [1:0] w139; f3_mult m140 (a[25:24], b[3:2], w139);
725
wire [1:0] w141; f3_add a142 ({w13[0], w13[1]}, w135, w141);
726
wire [1:0] w143; f3_add a144 (w141, w137, w143);
727
wire [1:0] w145; f3_add a146 (w143, w139, w145);
728
assign c[27:26] = w145;
729
wire [1:0] w147; f3_mult m148 (a[29:28], b[1:0], w147);
730
wire [1:0] w149; f3_mult m150 (a[27:26], b[3:2], w149);
731
wire [1:0] w151; f3_mult m152 (a[25:24], b[5:4], w151);
732
wire [1:0] w153; f3_add a154 (w147, w149, w153);
733
wire [1:0] w155; f3_add a156 (w153, w151, w155);
734
assign c[29:28] = w155;
735
wire [1:0] w157; f3_mult m158 (a[29:28], b[3:2], w157);
736
wire [1:0] w159; f3_mult m160 (a[31:30], b[1:0], w159);
737
wire [1:0] w161; f3_mult m162 (a[27:26], b[5:4], w161);
738
wire [1:0] w163; f3_add a164 (w157, w159, w163);
739
wire [1:0] w165; f3_add a166 (w163, w161, w165);
740
assign c[31:30] = w165;
741
wire [1:0] w167; f3_mult m168 (a[29:28], b[5:4], w167);
742
wire [1:0] w169; f3_mult m170 (a[31:30], b[3:2], w169);
743
wire [1:0] w171; f3_mult m172 (a[33:32], b[1:0], w171);
744
wire [1:0] w173; f3_add a174 (w167, w169, w173);
745
wire [1:0] w175; f3_add a176 (w173, w171, w175);
746
assign c[33:32] = w175;
747
wire [1:0] w177; f3_mult m178 (a[31:30], b[5:4], w177);
748
wire [1:0] w179; f3_mult m180 (a[35:34], b[1:0], w179);
749
wire [1:0] w181; f3_mult m182 (a[33:32], b[3:2], w181);
750
wire [1:0] w183; f3_add a184 (w177, w179, w183);
751
wire [1:0] w185; f3_add a186 (w183, w181, w185);
752
assign c[35:34] = w185;
753
wire [1:0] w187; f3_mult m188 (a[37:36], b[1:0], w187);
754
wire [1:0] w189; f3_mult m190 (a[33:32], b[5:4], w189);
755
wire [1:0] w191; f3_mult m192 (a[35:34], b[3:2], w191);
756
wire [1:0] w193; f3_add a194 (w187, w189, w193);
757
wire [1:0] w195; f3_add a196 (w193, w191, w195);
758
assign c[37:36] = w195;
759
wire [1:0] w197; f3_mult m198 (a[39:38], b[1:0], w197);
760
wire [1:0] w199; f3_mult m200 (a[35:34], b[5:4], w199);
761
wire [1:0] w201; f3_mult m202 (a[37:36], b[3:2], w201);
762
wire [1:0] w203; f3_add a204 (w197, w199, w203);
763
wire [1:0] w205; f3_add a206 (w203, w201, w205);
764
assign c[39:38] = w205;
765
wire [1:0] w207; f3_mult m208 (a[39:38], b[3:2], w207);
766
wire [1:0] w209; f3_mult m210 (a[41:40], b[1:0], w209);
767
wire [1:0] w211; f3_mult m212 (a[37:36], b[5:4], w211);
768
wire [1:0] w213; f3_add a214 (w207, w209, w213);
769
wire [1:0] w215; f3_add a216 (w213, w211, w215);
770
assign c[41:40] = w215;
771
wire [1:0] w217; f3_mult m218 (a[43:42], b[1:0], w217);
772
wire [1:0] w219; f3_mult m220 (a[39:38], b[5:4], w219);
773
wire [1:0] w221; f3_mult m222 (a[41:40], b[3:2], w221);
774
wire [1:0] w223; f3_add a224 (w217, w219, w223);
775
wire [1:0] w225; f3_add a226 (w223, w221, w225);
776
assign c[43:42] = w225;
777
wire [1:0] w227; f3_mult m228 (a[45:44], b[1:0], w227);
778
wire [1:0] w229; f3_mult m230 (a[43:42], b[3:2], w229);
779
wire [1:0] w231; f3_mult m232 (a[41:40], b[5:4], w231);
780
wire [1:0] w233; f3_add a234 (w227, w229, w233);
781
wire [1:0] w235; f3_add a236 (w233, w231, w235);
782
assign c[45:44] = w235;
783
wire [1:0] w237; f3_mult m238 (a[45:44], b[3:2], w237);
784
wire [1:0] w239; f3_mult m240 (a[47:46], b[1:0], w239);
785
wire [1:0] w241; f3_mult m242 (a[43:42], b[5:4], w241);
786
wire [1:0] w243; f3_add a244 (w237, w239, w243);
787
wire [1:0] w245; f3_add a246 (w243, w241, w245);
788
assign c[47:46] = w245;
789
wire [1:0] w247; f3_mult m248 (a[45:44], b[5:4], w247);
790
wire [1:0] w249; f3_mult m250 (a[47:46], b[3:2], w249);
791
wire [1:0] w251; f3_mult m252 (a[49:48], b[1:0], w251);
792
wire [1:0] w253; f3_add a254 (w247, w249, w253);
793
wire [1:0] w255; f3_add a256 (w253, w251, w255);
794
assign c[49:48] = w255;
795
wire [1:0] w257; f3_mult m258 (a[47:46], b[5:4], w257);
796
wire [1:0] w259; f3_mult m260 (a[51:50], b[1:0], w259);
797
wire [1:0] w261; f3_mult m262 (a[49:48], b[3:2], w261);
798
wire [1:0] w263; f3_add a264 (w257, w259, w263);
799
wire [1:0] w265; f3_add a266 (w263, w261, w265);
800
assign c[51:50] = w265;
801
wire [1:0] w267; f3_mult m268 (a[53:52], b[1:0], w267);
802
wire [1:0] w269; f3_mult m270 (a[49:48], b[5:4], w269);
803
wire [1:0] w271; f3_mult m272 (a[51:50], b[3:2], w271);
804
wire [1:0] w273; f3_add a274 (w267, w269, w273);
805
wire [1:0] w275; f3_add a276 (w273, w271, w275);
806
assign c[53:52] = w275;
807
wire [1:0] w277; f3_mult m278 (a[55:54], b[1:0], w277);
808
wire [1:0] w279; f3_mult m280 (a[51:50], b[5:4], w279);
809
wire [1:0] w281; f3_mult m282 (a[53:52], b[3:2], w281);
810
wire [1:0] w283; f3_add a284 (w277, w279, w283);
811
wire [1:0] w285; f3_add a286 (w283, w281, w285);
812
assign c[55:54] = w285;
813
wire [1:0] w287; f3_mult m288 (a[55:54], b[3:2], w287);
814
wire [1:0] w289; f3_mult m290 (a[57:56], b[1:0], w289);
815
wire [1:0] w291; f3_mult m292 (a[53:52], b[5:4], w291);
816
wire [1:0] w293; f3_add a294 (w287, w289, w293);
817
wire [1:0] w295; f3_add a296 (w293, w291, w295);
818
assign c[57:56] = w295;
819
wire [1:0] w297; f3_mult m298 (a[59:58], b[1:0], w297);
820
wire [1:0] w299; f3_mult m300 (a[55:54], b[5:4], w299);
821
wire [1:0] w301; f3_mult m302 (a[57:56], b[3:2], w301);
822
wire [1:0] w303; f3_add a304 (w297, w299, w303);
823
wire [1:0] w305; f3_add a306 (w303, w301, w305);
824
assign c[59:58] = w305;
825
wire [1:0] w307; f3_mult m308 (a[61:60], b[1:0], w307);
826
wire [1:0] w309; f3_mult m310 (a[59:58], b[3:2], w309);
827
wire [1:0] w311; f3_mult m312 (a[57:56], b[5:4], w311);
828
wire [1:0] w313; f3_add a314 (w307, w309, w313);
829
wire [1:0] w315; f3_add a316 (w313, w311, w315);
830
assign c[61:60] = w315;
831
wire [1:0] w317; f3_mult m318 (a[61:60], b[3:2], w317);
832
wire [1:0] w319; f3_mult m320 (a[63:62], b[1:0], w319);
833
wire [1:0] w321; f3_mult m322 (a[59:58], b[5:4], w321);
834
wire [1:0] w323; f3_add a324 (w317, w319, w323);
835
wire [1:0] w325; f3_add a326 (w323, w321, w325);
836
assign c[63:62] = w325;
837
wire [1:0] w327; f3_mult m328 (a[61:60], b[5:4], w327);
838
wire [1:0] w329; f3_mult m330 (a[63:62], b[3:2], w329);
839
wire [1:0] w331; f3_mult m332 (a[65:64], b[1:0], w331);
840
wire [1:0] w333; f3_add a334 (w327, w329, w333);
841
wire [1:0] w335; f3_add a336 (w333, w331, w335);
842
assign c[65:64] = w335;
843
wire [1:0] w337; f3_mult m338 (a[67:66], b[1:0], w337);
844
wire [1:0] w339; f3_mult m340 (a[63:62], b[5:4], w339);
845
wire [1:0] w341; f3_mult m342 (a[65:64], b[3:2], w341);
846
wire [1:0] w343; f3_add a344 (w337, w339, w343);
847
wire [1:0] w345; f3_add a346 (w343, w341, w345);
848
assign c[67:66] = w345;
849
wire [1:0] w347; f3_mult m348 (a[69:68], b[1:0], w347);
850
wire [1:0] w349; f3_mult m350 (a[65:64], b[5:4], w349);
851
wire [1:0] w351; f3_mult m352 (a[67:66], b[3:2], w351);
852
wire [1:0] w353; f3_add a354 (w347, w349, w353);
853
wire [1:0] w355; f3_add a356 (w353, w351, w355);
854
assign c[69:68] = w355;
855
wire [1:0] w357; f3_mult m358 (a[71:70], b[1:0], w357);
856
wire [1:0] w359; f3_mult m360 (a[67:66], b[5:4], w359);
857
wire [1:0] w361; f3_mult m362 (a[69:68], b[3:2], w361);
858
wire [1:0] w363; f3_add a364 (w357, w359, w363);
859
wire [1:0] w365; f3_add a366 (w363, w361, w365);
860
assign c[71:70] = w365;
861
wire [1:0] w367; f3_mult m368 (a[71:70], b[3:2], w367);
862
wire [1:0] w369; f3_mult m370 (a[73:72], b[1:0], w369);
863
wire [1:0] w371; f3_mult m372 (a[69:68], b[5:4], w371);
864
wire [1:0] w373; f3_add a374 (w367, w369, w373);
865
wire [1:0] w375; f3_add a376 (w373, w371, w375);
866
assign c[73:72] = w375;
867
wire [1:0] w377; f3_mult m378 (a[75:74], b[1:0], w377);
868
wire [1:0] w379; f3_mult m380 (a[71:70], b[5:4], w379);
869
wire [1:0] w381; f3_mult m382 (a[73:72], b[3:2], w381);
870
wire [1:0] w383; f3_add a384 (w377, w379, w383);
871
wire [1:0] w385; f3_add a386 (w383, w381, w385);
872
assign c[75:74] = w385;
873
wire [1:0] w387; f3_mult m388 (a[77:76], b[1:0], w387);
874
wire [1:0] w389; f3_mult m390 (a[75:74], b[3:2], w389);
875
wire [1:0] w391; f3_mult m392 (a[73:72], b[5:4], w391);
876
wire [1:0] w393; f3_add a394 (w387, w389, w393);
877
wire [1:0] w395; f3_add a396 (w393, w391, w395);
878
assign c[77:76] = w395;
879
wire [1:0] w397; f3_mult m398 (a[77:76], b[3:2], w397);
880
wire [1:0] w399; f3_mult m400 (a[79:78], b[1:0], w399);
881
wire [1:0] w401; f3_mult m402 (a[75:74], b[5:4], w401);
882
wire [1:0] w403; f3_add a404 (w397, w399, w403);
883
wire [1:0] w405; f3_add a406 (w403, w401, w405);
884
assign c[79:78] = w405;
885
wire [1:0] w407; f3_mult m408 (a[77:76], b[5:4], w407);
886
wire [1:0] w409; f3_mult m410 (a[79:78], b[3:2], w409);
887
wire [1:0] w411; f3_mult m412 (a[81:80], b[1:0], w411);
888
wire [1:0] w413; f3_add a414 (w407, w409, w413);
889
wire [1:0] w415; f3_add a416 (w413, w411, w415);
890
assign c[81:80] = w415;
891
wire [1:0] w417; f3_mult m418 (a[83:82], b[1:0], w417);
892
wire [1:0] w419; f3_mult m420 (a[79:78], b[5:4], w419);
893
wire [1:0] w421; f3_mult m422 (a[81:80], b[3:2], w421);
894
wire [1:0] w423; f3_add a424 (w417, w419, w423);
895
wire [1:0] w425; f3_add a426 (w423, w421, w425);
896
assign c[83:82] = w425;
897
wire [1:0] w427; f3_mult m428 (a[85:84], b[1:0], w427);
898
wire [1:0] w429; f3_mult m430 (a[81:80], b[5:4], w429);
899
wire [1:0] w431; f3_mult m432 (a[83:82], b[3:2], w431);
900
wire [1:0] w433; f3_add a434 (w427, w429, w433);
901
wire [1:0] w435; f3_add a436 (w433, w431, w435);
902
assign c[85:84] = w435;
903
wire [1:0] w437; f3_mult m438 (a[87:86], b[1:0], w437);
904
wire [1:0] w439; f3_mult m440 (a[83:82], b[5:4], w439);
905
wire [1:0] w441; f3_mult m442 (a[85:84], b[3:2], w441);
906
wire [1:0] w443; f3_add a444 (w437, w439, w443);
907
wire [1:0] w445; f3_add a446 (w443, w441, w445);
908
assign c[87:86] = w445;
909
wire [1:0] w447; f3_mult m448 (a[87:86], b[3:2], w447);
910
wire [1:0] w449; f3_mult m450 (a[89:88], b[1:0], w449);
911
wire [1:0] w451; f3_mult m452 (a[85:84], b[5:4], w451);
912
wire [1:0] w453; f3_add a454 (w447, w449, w453);
913
wire [1:0] w455; f3_add a456 (w453, w451, w455);
914
assign c[89:88] = w455;
915
wire [1:0] w457; f3_mult m458 (a[91:90], b[1:0], w457);
916
wire [1:0] w459; f3_mult m460 (a[87:86], b[5:4], w459);
917
wire [1:0] w461; f3_mult m462 (a[89:88], b[3:2], w461);
918
wire [1:0] w463; f3_add a464 (w457, w459, w463);
919
wire [1:0] w465; f3_add a466 (w463, w461, w465);
920
assign c[91:90] = w465;
921
wire [1:0] w467; f3_mult m468 (a[91:90], b[3:2], w467);
922
wire [1:0] w469; f3_mult m470 (a[89:88], b[5:4], w469);
923
wire [1:0] w471; f3_mult m472 (a[93:92], b[1:0], w471);
924
wire [1:0] w473; f3_add a474 (w467, w469, w473);
925
wire [1:0] w475; f3_add a476 (w473, w471, w475);
926
assign c[93:92] = w475;
927
wire [1:0] w477; f3_mult m478 (a[93:92], b[3:2], w477);
928
wire [1:0] w479; f3_mult m480 (a[95:94], b[1:0], w479);
929
wire [1:0] w481; f3_mult m482 (a[91:90], b[5:4], w481);
930
wire [1:0] w483; f3_add a484 (w477, w479, w483);
931
wire [1:0] w485; f3_add a486 (w483, w481, w485);
932
assign c[95:94] = w485;
933
wire [1:0] w487; f3_mult m488 (a[93:92], b[5:4], w487);
934
wire [1:0] w489; f3_mult m490 (a[95:94], b[3:2], w489);
935
wire [1:0] w491; f3_mult m492 (a[97:96], b[1:0], w491);
936
wire [1:0] w493; f3_add a494 (w487, w489, w493);
937
wire [1:0] w495; f3_add a496 (w493, w491, w495);
938
assign c[97:96] = w495;
939
wire [1:0] w497; f3_mult m498 (a[99:98], b[1:0], w497);
940
wire [1:0] w499; f3_mult m500 (a[95:94], b[5:4], w499);
941
wire [1:0] w501; f3_mult m502 (a[97:96], b[3:2], w501);
942
wire [1:0] w503; f3_add a504 (w497, w499, w503);
943
wire [1:0] w505; f3_add a506 (w503, w501, w505);
944
assign c[99:98] = w505;
945
wire [1:0] w507; f3_mult m508 (a[101:100], b[1:0], w507);
946
wire [1:0] w509; f3_mult m510 (a[97:96], b[5:4], w509);
947
wire [1:0] w511; f3_mult m512 (a[99:98], b[3:2], w511);
948
wire [1:0] w513; f3_add a514 (w507, w509, w513);
949
wire [1:0] w515; f3_add a516 (w513, w511, w515);
950
assign c[101:100] = w515;
951
wire [1:0] w517; f3_mult m518 (a[103:102], b[1:0], w517);
952
wire [1:0] w519; f3_mult m520 (a[99:98], b[5:4], w519);
953
wire [1:0] w521; f3_mult m522 (a[101:100], b[3:2], w521);
954
wire [1:0] w523; f3_add a524 (w517, w519, w523);
955
wire [1:0] w525; f3_add a526 (w523, w521, w525);
956
assign c[103:102] = w525;
957
wire [1:0] w527; f3_mult m528 (a[103:102], b[3:2], w527);
958
wire [1:0] w529; f3_mult m530 (a[105:104], b[1:0], w529);
959
wire [1:0] w531; f3_mult m532 (a[101:100], b[5:4], w531);
960
wire [1:0] w533; f3_add a534 (w527, w529, w533);
961
wire [1:0] w535; f3_add a536 (w533, w531, w535);
962
assign c[105:104] = w535;
963
wire [1:0] w537; f3_mult m538 (a[107:106], b[1:0], w537);
964
wire [1:0] w539; f3_mult m540 (a[103:102], b[5:4], w539);
965
wire [1:0] w541; f3_mult m542 (a[105:104], b[3:2], w541);
966
wire [1:0] w543; f3_add a544 (w537, w539, w543);
967
wire [1:0] w545; f3_add a546 (w543, w541, w545);
968
assign c[107:106] = w545;
969
wire [1:0] w547; f3_mult m548 (a[107:106], b[3:2], w547);
970
wire [1:0] w549; f3_mult m550 (a[105:104], b[5:4], w549);
971
wire [1:0] w551; f3_mult m552 (a[109:108], b[1:0], w551);
972
wire [1:0] w553; f3_add a554 (w547, w549, w553);
973
wire [1:0] w555; f3_add a556 (w553, w551, w555);
974
assign c[109:108] = w555;
975
wire [1:0] w557; f3_mult m558 (a[109:108], b[3:2], w557);
976
wire [1:0] w559; f3_mult m560 (a[111:110], b[1:0], w559);
977
wire [1:0] w561; f3_mult m562 (a[107:106], b[5:4], w561);
978
wire [1:0] w563; f3_add a564 (w557, w559, w563);
979
wire [1:0] w565; f3_add a566 (w563, w561, w565);
980
assign c[111:110] = w565;
981
wire [1:0] w567; f3_mult m568 (a[109:108], b[5:4], w567);
982
wire [1:0] w569; f3_mult m570 (a[111:110], b[3:2], w569);
983
wire [1:0] w571; f3_mult m572 (a[113:112], b[1:0], w571);
984
wire [1:0] w573; f3_add a574 (w567, w569, w573);
985
wire [1:0] w575; f3_add a576 (w573, w571, w575);
986
assign c[113:112] = w575;
987
wire [1:0] w577; f3_mult m578 (a[115:114], b[1:0], w577);
988
wire [1:0] w579; f3_mult m580 (a[111:110], b[5:4], w579);
989
wire [1:0] w581; f3_mult m582 (a[113:112], b[3:2], w581);
990
wire [1:0] w583; f3_add a584 (w577, w579, w583);
991
wire [1:0] w585; f3_add a586 (w583, w581, w585);
992
assign c[115:114] = w585;
993
wire [1:0] w587; f3_mult m588 (a[117:116], b[1:0], w587);
994
wire [1:0] w589; f3_mult m590 (a[113:112], b[5:4], w589);
995
wire [1:0] w591; f3_mult m592 (a[115:114], b[3:2], w591);
996
wire [1:0] w593; f3_add a594 (w587, w589, w593);
997
wire [1:0] w595; f3_add a596 (w593, w591, w595);
998
assign c[117:116] = w595;
999
wire [1:0] w597; f3_mult m598 (a[119:118], b[1:0], w597);
1000
wire [1:0] w599; f3_mult m600 (a[115:114], b[5:4], w599);
1001
wire [1:0] w601; f3_mult m602 (a[117:116], b[3:2], w601);
1002
wire [1:0] w603; f3_add a604 (w597, w599, w603);
1003
wire [1:0] w605; f3_add a606 (w603, w601, w605);
1004
assign c[119:118] = w605;
1005
wire [1:0] w607; f3_mult m608 (a[119:118], b[3:2], w607);
1006
wire [1:0] w609; f3_mult m610 (a[121:120], b[1:0], w609);
1007
wire [1:0] w611; f3_mult m612 (a[117:116], b[5:4], w611);
1008
wire [1:0] w613; f3_add a614 (w607, w609, w613);
1009
wire [1:0] w615; f3_add a616 (w613, w611, w615);
1010
assign c[121:120] = w615;
1011
wire [1:0] w617; f3_mult m618 (a[123:122], b[1:0], w617);
1012
wire [1:0] w619; f3_mult m620 (a[119:118], b[5:4], w619);
1013
wire [1:0] w621; f3_mult m622 (a[121:120], b[3:2], w621);
1014
wire [1:0] w623; f3_add a624 (w617, w619, w623);
1015
wire [1:0] w625; f3_add a626 (w623, w621, w625);
1016
assign c[123:122] = w625;
1017
wire [1:0] w627; f3_mult m628 (a[123:122], b[3:2], w627);
1018
wire [1:0] w629; f3_mult m630 (a[121:120], b[5:4], w629);
1019
wire [1:0] w631; f3_mult m632 (a[125:124], b[1:0], w631);
1020
wire [1:0] w633; f3_add a634 (w627, w629, w633);
1021
wire [1:0] w635; f3_add a636 (w633, w631, w635);
1022
assign c[125:124] = w635;
1023
wire [1:0] w637; f3_mult m638 (a[125:124], b[3:2], w637);
1024
wire [1:0] w639; f3_mult m640 (a[127:126], b[1:0], w639);
1025
wire [1:0] w641; f3_mult m642 (a[123:122], b[5:4], w641);
1026
wire [1:0] w643; f3_add a644 (w637, w639, w643);
1027
wire [1:0] w645; f3_add a646 (w643, w641, w645);
1028
assign c[127:126] = w645;
1029
wire [1:0] w647; f3_mult m648 (a[125:124], b[5:4], w647);
1030
wire [1:0] w649; f3_mult m650 (a[127:126], b[3:2], w649);
1031
wire [1:0] w651; f3_mult m652 (a[129:128], b[1:0], w651);
1032
wire [1:0] w653; f3_add a654 (w647, w649, w653);
1033
wire [1:0] w655; f3_add a656 (w653, w651, w655);
1034
assign c[129:128] = w655;
1035
wire [1:0] w657; f3_mult m658 (a[127:126], b[5:4], w657);
1036
wire [1:0] w659; f3_mult m660 (a[131:130], b[1:0], w659);
1037
wire [1:0] w661; f3_mult m662 (a[129:128], b[3:2], w661);
1038
wire [1:0] w663; f3_add a664 (w657, w659, w663);
1039
wire [1:0] w665; f3_add a666 (w663, w661, w665);
1040
assign c[131:130] = w665;
1041
wire [1:0] w667; f3_mult m668 (a[133:132], b[1:0], w667);
1042
wire [1:0] w669; f3_mult m670 (a[129:128], b[5:4], w669);
1043
wire [1:0] w671; f3_mult m672 (a[131:130], b[3:2], w671);
1044
wire [1:0] w673; f3_add a674 (w667, w669, w673);
1045
wire [1:0] w675; f3_add a676 (w673, w671, w675);
1046
assign c[133:132] = w675;
1047
wire [1:0] w677; f3_mult m678 (a[133:132], b[3:2], w677);
1048
wire [1:0] w679; f3_mult m680 (a[131:130], b[5:4], w679);
1049
wire [1:0] w681; f3_mult m682 (a[135:134], b[1:0], w681);
1050
wire [1:0] w683; f3_add a684 (w677, w679, w683);
1051
wire [1:0] w685; f3_add a686 (w683, w681, w685);
1052
assign c[135:134] = w685;
1053
wire [1:0] w687; f3_mult m688 (a[135:134], b[3:2], w687);
1054
wire [1:0] w689; f3_mult m690 (a[137:136], b[1:0], w689);
1055
wire [1:0] w691; f3_mult m692 (a[133:132], b[5:4], w691);
1056
wire [1:0] w693; f3_add a694 (w687, w689, w693);
1057
wire [1:0] w695; f3_add a696 (w693, w691, w695);
1058
assign c[137:136] = w695;
1059
wire [1:0] w697; f3_mult m698 (a[139:138], b[1:0], w697);
1060
wire [1:0] w699; f3_mult m700 (a[135:134], b[5:4], w699);
1061
wire [1:0] w701; f3_mult m702 (a[137:136], b[3:2], w701);
1062
wire [1:0] w703; f3_add a704 (w697, w699, w703);
1063
wire [1:0] w705; f3_add a706 (w703, w701, w705);
1064
assign c[139:138] = w705;
1065
wire [1:0] w707; f3_mult m708 (a[141:140], b[1:0], w707);
1066
wire [1:0] w709; f3_mult m710 (a[139:138], b[3:2], w709);
1067
wire [1:0] w711; f3_mult m712 (a[137:136], b[5:4], w711);
1068
wire [1:0] w713; f3_add a714 (w707, w709, w713);
1069
wire [1:0] w715; f3_add a716 (w713, w711, w715);
1070
assign c[141:140] = w715;
1071
wire [1:0] w717; f3_mult m718 (a[143:142], b[1:0], w717);
1072
wire [1:0] w719; f3_mult m720 (a[141:140], b[3:2], w719);
1073
wire [1:0] w721; f3_mult m722 (a[139:138], b[5:4], w721);
1074
wire [1:0] w723; f3_add a724 (w717, w719, w723);
1075
wire [1:0] w725; f3_add a726 (w723, w721, w725);
1076
assign c[143:142] = w725;
1077
wire [1:0] w727; f3_mult m728 (a[141:140], b[5:4], w727);
1078
wire [1:0] w729; f3_mult m730 (a[143:142], b[3:2], w729);
1079
wire [1:0] w731; f3_mult m732 (a[145:144], b[1:0], w731);
1080
wire [1:0] w733; f3_add a734 (w727, w729, w733);
1081
wire [1:0] w735; f3_add a736 (w733, w731, w735);
1082
assign c[145:144] = w735;
1083
wire [1:0] w737; f3_mult m738 (a[143:142], b[5:4], w737);
1084
wire [1:0] w739; f3_mult m740 (a[147:146], b[1:0], w739);
1085
wire [1:0] w741; f3_mult m742 (a[145:144], b[3:2], w741);
1086
wire [1:0] w743; f3_add a744 (w737, w739, w743);
1087
wire [1:0] w745; f3_add a746 (w743, w741, w745);
1088
assign c[147:146] = w745;
1089
wire [1:0] w747; f3_mult m748 (a[145:144], b[5:4], w747);
1090
wire [1:0] w749; f3_mult m750 (a[149:148], b[1:0], w749);
1091
wire [1:0] w751; f3_mult m752 (a[147:146], b[3:2], w751);
1092
wire [1:0] w753; f3_add a754 (w747, w749, w753);
1093
wire [1:0] w755; f3_add a756 (w753, w751, w755);
1094
assign c[149:148] = w755;
1095
wire [1:0] w757; f3_mult m758 (a[149:148], b[3:2], w757);
1096
wire [1:0] w759; f3_mult m760 (a[147:146], b[5:4], w759);
1097
wire [1:0] w761; f3_mult m762 (a[151:150], b[1:0], w761);
1098
wire [1:0] w763; f3_add a764 (w757, w759, w763);
1099
wire [1:0] w765; f3_add a766 (w763, w761, w765);
1100
assign c[151:150] = w765;
1101
wire [1:0] w767; f3_mult m768 (a[151:150], b[3:2], w767);
1102
wire [1:0] w769; f3_mult m770 (a[149:148], b[5:4], w769);
1103
wire [1:0] w771; f3_mult m772 (a[153:152], b[1:0], w771);
1104
wire [1:0] w773; f3_add a774 (w767, w769, w773);
1105
wire [1:0] w775; f3_add a776 (w773, w771, w775);
1106
assign c[153:152] = w775;
1107
wire [1:0] w777; f3_mult m778 (a[155:154], b[1:0], w777);
1108
wire [1:0] w779; f3_mult m780 (a[151:150], b[5:4], w779);
1109
wire [1:0] w781; f3_mult m782 (a[153:152], b[3:2], w781);
1110
wire [1:0] w783; f3_add a784 (w777, w779, w783);
1111
wire [1:0] w785; f3_add a786 (w783, w781, w785);
1112
assign c[155:154] = w785;
1113
wire [1:0] w787; f3_mult m788 (a[155:154], b[3:2], w787);
1114
wire [1:0] w789; f3_mult m790 (a[153:152], b[5:4], w789);
1115
wire [1:0] w791; f3_mult m792 (a[157:156], b[1:0], w791);
1116
wire [1:0] w793; f3_add a794 (w787, w789, w793);
1117
wire [1:0] w795; f3_add a796 (w793, w791, w795);
1118
assign c[157:156] = w795;
1119
wire [1:0] w797; f3_mult m798 (a[159:158], b[1:0], w797);
1120
wire [1:0] w799; f3_mult m800 (a[157:156], b[3:2], w799);
1121
wire [1:0] w801; f3_mult m802 (a[155:154], b[5:4], w801);
1122
wire [1:0] w803; f3_add a804 (w797, w799, w803);
1123
wire [1:0] w805; f3_add a806 (w803, w801, w805);
1124
assign c[159:158] = w805;
1125
wire [1:0] w807; f3_mult m808 (a[157:156], b[5:4], w807);
1126
wire [1:0] w809; f3_mult m810 (a[159:158], b[3:2], w809);
1127
wire [1:0] w811; f3_mult m812 (a[161:160], b[1:0], w811);
1128
wire [1:0] w813; f3_add a814 (w807, w809, w813);
1129
wire [1:0] w815; f3_add a816 (w813, w811, w815);
1130
assign c[161:160] = w815;
1131
wire [1:0] w817; f3_mult m818 (a[159:158], b[5:4], w817);
1132
wire [1:0] w819; f3_mult m820 (a[163:162], b[1:0], w819);
1133
wire [1:0] w821; f3_mult m822 (a[161:160], b[3:2], w821);
1134
wire [1:0] w823; f3_add a824 (w817, w819, w823);
1135
wire [1:0] w825; f3_add a826 (w823, w821, w825);
1136
assign c[163:162] = w825;
1137
wire [1:0] w827; f3_mult m828 (a[161:160], b[5:4], w827);
1138
wire [1:0] w829; f3_mult m830 (a[165:164], b[1:0], w829);
1139
wire [1:0] w831; f3_mult m832 (a[163:162], b[3:2], w831);
1140
wire [1:0] w833; f3_add a834 (w827, w829, w833);
1141
wire [1:0] w835; f3_add a836 (w833, w831, w835);
1142
assign c[165:164] = w835;
1143
wire [1:0] w837; f3_mult m838 (a[165:164], b[3:2], w837);
1144
wire [1:0] w839; f3_mult m840 (a[163:162], b[5:4], w839);
1145
wire [1:0] w841; f3_mult m842 (a[167:166], b[1:0], w841);
1146
wire [1:0] w843; f3_add a844 (w837, w839, w843);
1147
wire [1:0] w845; f3_add a846 (w843, w841, w845);
1148
assign c[167:166] = w845;
1149
wire [1:0] w847; f3_mult m848 (a[167:166], b[3:2], w847);
1150
wire [1:0] w849; f3_mult m850 (a[165:164], b[5:4], w849);
1151
wire [1:0] w851; f3_mult m852 (a[169:168], b[1:0], w851);
1152
wire [1:0] w853; f3_add a854 (w847, w849, w853);
1153
wire [1:0] w855; f3_add a856 (w853, w851, w855);
1154
assign c[169:168] = w855;
1155
wire [1:0] w857; f3_mult m858 (a[171:170], b[1:0], w857);
1156
wire [1:0] w859; f3_mult m860 (a[167:166], b[5:4], w859);
1157
wire [1:0] w861; f3_mult m862 (a[169:168], b[3:2], w861);
1158
wire [1:0] w863; f3_add a864 (w857, w859, w863);
1159
wire [1:0] w865; f3_add a866 (w863, w861, w865);
1160
assign c[171:170] = w865;
1161
wire [1:0] w867; f3_mult m868 (a[171:170], b[3:2], w867);
1162
wire [1:0] w869; f3_mult m870 (a[169:168], b[5:4], w869);
1163
wire [1:0] w871; f3_mult m872 (a[173:172], b[1:0], w871);
1164
wire [1:0] w873; f3_add a874 (w867, w869, w873);
1165
wire [1:0] w875; f3_add a876 (w873, w871, w875);
1166
assign c[173:172] = w875;
1167
wire [1:0] w877; f3_mult m878 (a[173:172], b[3:2], w877);
1168
wire [1:0] w879; f3_mult m880 (a[175:174], b[1:0], w879);
1169
wire [1:0] w881; f3_mult m882 (a[171:170], b[5:4], w881);
1170
wire [1:0] w883; f3_add a884 (w877, w879, w883);
1171
wire [1:0] w885; f3_add a886 (w883, w881, w885);
1172
assign c[175:174] = w885;
1173
wire [1:0] w887; f3_mult m888 (a[173:172], b[5:4], w887);
1174
wire [1:0] w889; f3_mult m890 (a[175:174], b[3:2], w889);
1175
wire [1:0] w891; f3_mult m892 (a[177:176], b[1:0], w891);
1176
wire [1:0] w893; f3_add a894 (w887, w889, w893);
1177
wire [1:0] w895; f3_add a896 (w893, w891, w895);
1178
assign c[177:176] = w895;
1179
wire [1:0] w897; f3_mult m898 (a[175:174], b[5:4], w897);
1180
wire [1:0] w899; f3_mult m900 (a[179:178], b[1:0], w899);
1181
wire [1:0] w901; f3_mult m902 (a[177:176], b[3:2], w901);
1182
wire [1:0] w903; f3_add a904 (w897, w899, w903);
1183
wire [1:0] w905; f3_add a906 (w903, w901, w905);
1184
assign c[179:178] = w905;
1185
wire [1:0] w907; f3_mult m908 (a[177:176], b[5:4], w907);
1186
wire [1:0] w909; f3_mult m910 (a[181:180], b[1:0], w909);
1187
wire [1:0] w911; f3_mult m912 (a[179:178], b[3:2], w911);
1188
wire [1:0] w913; f3_add a914 (w907, w909, w913);
1189
wire [1:0] w915; f3_add a916 (w913, w911, w915);
1190
assign c[181:180] = w915;
1191
wire [1:0] w917; f3_mult m918 (a[181:180], b[3:2], w917);
1192
wire [1:0] w919; f3_mult m920 (a[183:182], b[1:0], w919);
1193
wire [1:0] w921; f3_mult m922 (a[179:178], b[5:4], w921);
1194
wire [1:0] w923; f3_add a924 (w917, w919, w923);
1195
wire [1:0] w925; f3_add a926 (w923, w921, w925);
1196
assign c[183:182] = w925;
1197
wire [1:0] w927; f3_mult m928 (a[183:182], b[3:2], w927);
1198
wire [1:0] w929; f3_mult m930 (a[181:180], b[5:4], w929);
1199
wire [1:0] w931; f3_mult m932 (a[185:184], b[1:0], w931);
1200
wire [1:0] w933; f3_add a934 (w927, w929, w933);
1201
wire [1:0] w935; f3_add a936 (w933, w931, w935);
1202
assign c[185:184] = w935;
1203
wire [1:0] w937; f3_mult m938 (a[187:186], b[1:0], w937);
1204
wire [1:0] w939; f3_mult m940 (a[183:182], b[5:4], w939);
1205
wire [1:0] w941; f3_mult m942 (a[185:184], b[3:2], w941);
1206
wire [1:0] w943; f3_add a944 (w937, w939, w943);
1207
wire [1:0] w945; f3_add a946 (w943, w941, w945);
1208
assign c[187:186] = w945;
1209
wire [1:0] w947; f3_mult m948 (a[187:186], b[3:2], w947);
1210
wire [1:0] w949; f3_mult m950 (a[185:184], b[5:4], w949);
1211
wire [1:0] w951; f3_mult m952 (a[189:188], b[1:0], w951);
1212
wire [1:0] w953; f3_add a954 (w947, w949, w953);
1213
wire [1:0] w955; f3_add a956 (w953, w951, w955);
1214
assign c[189:188] = w955;
1215
wire [1:0] w957; f3_mult m958 (a[189:188], b[3:2], w957);
1216
wire [1:0] w959; f3_mult m960 (a[191:190], b[1:0], w959);
1217
wire [1:0] w961; f3_mult m962 (a[187:186], b[5:4], w961);
1218
wire [1:0] w963; f3_add a964 (w957, w959, w963);
1219
wire [1:0] w965; f3_add a966 (w963, w961, w965);
1220
assign c[191:190] = w965;
1221
wire [1:0] w967; f3_mult m968 (a[189:188], b[5:4], w967);
1222
wire [1:0] w969; f3_mult m970 (a[191:190], b[3:2], w969);
1223
wire [1:0] w971; f3_mult m972 (a[193:192], b[1:0], w971);
1224
wire [1:0] w973; f3_add a974 (w967, w969, w973);
1225
wire [1:0] w975; f3_add a976 (w973, w971, w975);
1226
assign c[193:192] = w975;
1227
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.