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1 2 olivier.girard
//----------------------------------------------------------------------------
2
// Copyright (C) 2001 Authors
3
//
4
// This source file may be used and distributed without restriction provided
5
// that this copyright statement is not removed from the file and that any
6
// derivative work contains the original copyright notice and the associated
7
// disclaimer.
8
//
9
// This source file is free software; you can redistribute it and/or modify
10
// it under the terms of the GNU Lesser General Public License as published
11
// by the Free Software Foundation; either version 2.1 of the License, or
12
// (at your option) any later version.
13
//
14
// This source is distributed in the hope that it will be useful, but WITHOUT
15
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
18
//
19
// You should have received a copy of the GNU Lesser General Public License
20
// along with this source; if not, write to the Free Software Foundation,
21
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
22
//
23
//----------------------------------------------------------------------------
24
//
25 34 olivier.girard
// *File Name: omsp_gpio.v
26 2 olivier.girard
// 
27
// *Module Description:
28
//                       Digital I/O interface
29
//
30
// *Author(s):
31
//              - Olivier Girard,    olgirard@gmail.com
32
//
33
//----------------------------------------------------------------------------
34 17 olivier.girard
// $Rev: 79 $
35
// $LastChangedBy: olivier.girard $
36
// $LastChangedDate: 2010-11-23 20:36:16 +0100 (Tue, 23 Nov 2010) $
37
//----------------------------------------------------------------------------
38 23 olivier.girard
`include "timescale.v"
39
`include "openMSP430_defines.v"
40 2 olivier.girard
 
41 34 olivier.girard
module  omsp_gpio (
42 2 olivier.girard
 
43
// OUTPUTs
44
    irq_port1,                      // Port 1 interrupt
45
    irq_port2,                      // Port 2 interrupt
46
    p1_dout,                        // Port 1 data output
47
    p1_dout_en,                     // Port 1 data output enable
48
    p1_sel,                         // Port 1 function select
49
    p2_dout,                        // Port 2 data output
50
    p2_dout_en,                     // Port 2 data output enable
51
    p2_sel,                         // Port 2 function select
52
    p3_dout,                        // Port 3 data output
53
    p3_dout_en,                     // Port 3 data output enable
54
    p3_sel,                         // Port 3 function select
55
    p4_dout,                        // Port 4 data output
56
    p4_dout_en,                     // Port 4 data output enable
57
    p4_sel,                         // Port 4 function select
58
    p5_dout,                        // Port 5 data output
59
    p5_dout_en,                     // Port 5 data output enable
60
    p5_sel,                         // Port 5 function select
61
    p6_dout,                        // Port 6 data output
62
    p6_dout_en,                     // Port 6 data output enable
63
    p6_sel,                         // Port 6 function select
64
    per_dout,                       // Peripheral data output
65
 
66
// INPUTs
67
    mclk,                           // Main system clock
68
    p1_din,                         // Port 1 data input
69
    p2_din,                         // Port 2 data input
70
    p3_din,                         // Port 3 data input
71
    p4_din,                         // Port 4 data input
72
    p5_din,                         // Port 5 data input
73
    p6_din,                         // Port 6 data input
74
    per_addr,                       // Peripheral address
75
    per_din,                        // Peripheral data input
76
    per_en,                         // Peripheral enable (high active)
77
    per_wen,                        // Peripheral write enable (high active)
78
    puc                             // Main system reset
79
);
80
 
81
// PARAMETERs
82
//============
83
parameter           P1_EN = 1'b1;   // Enable Port 1
84
parameter           P2_EN = 1'b1;   // Enable Port 2
85
parameter           P3_EN = 1'b0;   // Enable Port 3
86
parameter           P4_EN = 1'b0;   // Enable Port 4
87
parameter           P5_EN = 1'b0;   // Enable Port 5
88
parameter           P6_EN = 1'b0;   // Enable Port 6
89
 
90
 
91
// OUTPUTs
92
//=========
93
output              irq_port1;      // Port 1 interrupt
94
output              irq_port2;      // Port 2 interrupt
95
output        [7:0] p1_dout;        // Port 1 data output
96
output        [7:0] p1_dout_en;     // Port 1 data output enable
97
output        [7:0] p1_sel;         // Port 1 function select
98
output        [7:0] p2_dout;        // Port 2 data output
99
output        [7:0] p2_dout_en;     // Port 2 data output enable
100
output        [7:0] p2_sel;         // Port 2 function select
101
output        [7:0] p3_dout;        // Port 3 data output
102
output        [7:0] p3_dout_en;     // Port 3 data output enable
103
output        [7:0] p3_sel;         // Port 3 function select
104
output        [7:0] p4_dout;        // Port 4 data output
105
output        [7:0] p4_dout_en;     // Port 4 data output enable
106
output        [7:0] p4_sel;         // Port 4 function select
107
output        [7:0] p5_dout;        // Port 5 data output
108
output        [7:0] p5_dout_en;     // Port 5 data output enable
109
output        [7:0] p5_sel;         // Port 5 function select
110
output        [7:0] p6_dout;        // Port 6 data output
111
output        [7:0] p6_dout_en;     // Port 6 data output enable
112
output        [7:0] p6_sel;         // Port 6 function select
113
output       [15:0] per_dout;       // Peripheral data output
114
 
115
// INPUTs
116
//=========
117
input               mclk;           // Main system clock
118
input         [7:0] p1_din;         // Port 1 data input
119
input         [7:0] p2_din;         // Port 2 data input
120
input         [7:0] p3_din;         // Port 3 data input
121
input         [7:0] p4_din;         // Port 4 data input
122
input         [7:0] p5_din;         // Port 5 data input
123
input         [7:0] p6_din;         // Port 6 data input
124
input         [7:0] per_addr;       // Peripheral address
125
input        [15:0] per_din;        // Peripheral data input
126
input               per_en;         // Peripheral enable (high active)
127
input         [1:0] per_wen;        // Peripheral write enable (high active)
128
input               puc;            // Main system reset
129
 
130
 
131
//=============================================================================
132
// 1)  PARAMETER DECLARATION
133
//=============================================================================
134
 
135
// Masks
136
parameter           P1_EN_MSK   = {8{P1_EN[0]}};
137
parameter           P2_EN_MSK   = {8{P2_EN[0]}};
138
parameter           P3_EN_MSK   = {8{P3_EN[0]}};
139
parameter           P4_EN_MSK   = {8{P4_EN[0]}};
140
parameter           P5_EN_MSK   = {8{P5_EN[0]}};
141
parameter           P6_EN_MSK   = {8{P6_EN[0]}};
142
 
143
// Register addresses
144
parameter           P1IN        = 9'h020;                  // Port 1
145
parameter           P1OUT       = 9'h021;
146
parameter           P1DIR       = 9'h022;
147
parameter           P1IFG       = 9'h023;
148
parameter           P1IES       = 9'h024;
149
parameter           P1IE        = 9'h025;
150
parameter           P1SEL       = 9'h026;
151
parameter           P2IN        = 9'h028;                  // Port 2
152
parameter           P2OUT       = 9'h029;
153
parameter           P2DIR       = 9'h02A;
154
parameter           P2IFG       = 9'h02B;
155
parameter           P2IES       = 9'h02C;
156
parameter           P2IE        = 9'h02D;
157
parameter           P2SEL       = 9'h02E;
158
parameter           P3IN        = 9'h018;                  // Port 3
159
parameter           P3OUT       = 9'h019;
160
parameter           P3DIR       = 9'h01A;
161
parameter           P3SEL       = 9'h01B;
162
parameter           P4IN        = 9'h01C;                  // Port 4
163
parameter           P4OUT       = 9'h01D;
164
parameter           P4DIR       = 9'h01E;
165
parameter           P4SEL       = 9'h01F;
166
parameter           P5IN        = 9'h030;                  // Port 5
167
parameter           P5OUT       = 9'h031;
168
parameter           P5DIR       = 9'h032;
169
parameter           P5SEL       = 9'h033;
170
parameter           P6IN        = 9'h034;                  // Port 6
171
parameter           P6OUT       = 9'h035;
172
parameter           P6DIR       = 9'h036;
173
parameter           P6SEL       = 9'h037;
174
 
175
 
176
// Register one-hot decoder
177
parameter           P1IN_D      = (256'h1 << (P1IN  /2));  // Port 1
178
parameter           P1OUT_D     = (256'h1 << (P1OUT /2));
179
parameter           P1DIR_D     = (256'h1 << (P1DIR /2));
180
parameter           P1IFG_D     = (256'h1 << (P1IFG /2));
181
parameter           P1IES_D     = (256'h1 << (P1IES /2));
182
parameter           P1IE_D      = (256'h1 << (P1IE  /2));
183
parameter           P1SEL_D     = (256'h1 << (P1SEL /2));
184
parameter           P2IN_D      = (256'h1 << (P2IN  /2));  // Port 2
185
parameter           P2OUT_D     = (256'h1 << (P2OUT /2));
186
parameter           P2DIR_D     = (256'h1 << (P2DIR /2));
187
parameter           P2IFG_D     = (256'h1 << (P2IFG /2));
188
parameter           P2IES_D     = (256'h1 << (P2IES /2));
189
parameter           P2IE_D      = (256'h1 << (P2IE  /2));
190
parameter           P2SEL_D     = (256'h1 << (P2SEL /2));
191
parameter           P3IN_D      = (256'h1 << (P3IN  /2));  // Port 3
192
parameter           P3OUT_D     = (256'h1 << (P3OUT /2));
193
parameter           P3DIR_D     = (256'h1 << (P3DIR /2));
194
parameter           P3SEL_D     = (256'h1 << (P3SEL /2));
195
parameter           P4IN_D      = (256'h1 << (P4IN  /2));  // Port 4
196
parameter           P4OUT_D     = (256'h1 << (P4OUT /2));
197
parameter           P4DIR_D     = (256'h1 << (P4DIR /2));
198
parameter           P4SEL_D     = (256'h1 << (P4SEL /2));
199
parameter           P5IN_D      = (256'h1 << (P5IN  /2));  // Port 5
200
parameter           P5OUT_D     = (256'h1 << (P5OUT /2));
201
parameter           P5DIR_D     = (256'h1 << (P5DIR /2));
202
parameter           P5SEL_D     = (256'h1 << (P5SEL /2));
203
parameter           P6IN_D      = (256'h1 << (P6IN  /2));  // Port 6
204
parameter           P6OUT_D     = (256'h1 << (P6OUT /2));
205
parameter           P6DIR_D     = (256'h1 << (P6DIR /2));
206
parameter           P6SEL_D     = (256'h1 << (P6SEL /2));
207
 
208
 
209
//============================================================================
210
// 2)  REGISTER DECODER
211
//============================================================================
212
 
213
// Register address decode
214
reg  [255:0]  reg_dec;
215
always @(per_addr)
216
  case (per_addr)
217
    (P1IN  /2):   reg_dec  =  P1IN_D   & {256{P1_EN[0]}};
218
    (P1OUT /2):   reg_dec  =  P1OUT_D  & {256{P1_EN[0]}};
219
    (P1DIR /2):   reg_dec  =  P1DIR_D  & {256{P1_EN[0]}};
220
    (P1IFG /2):   reg_dec  =  P1IFG_D  & {256{P1_EN[0]}};
221
    (P1IES /2):   reg_dec  =  P1IES_D  & {256{P1_EN[0]}};
222
    (P1IE  /2):   reg_dec  =  P1IE_D   & {256{P1_EN[0]}};
223
    (P1SEL /2):   reg_dec  =  P1SEL_D  & {256{P1_EN[0]}};
224
    (P2IN  /2):   reg_dec  =  P2IN_D   & {256{P2_EN[0]}};
225
    (P2OUT /2):   reg_dec  =  P2OUT_D  & {256{P2_EN[0]}};
226
    (P2DIR /2):   reg_dec  =  P2DIR_D  & {256{P2_EN[0]}};
227
    (P2IFG /2):   reg_dec  =  P2IFG_D  & {256{P2_EN[0]}};
228
    (P2IES /2):   reg_dec  =  P2IES_D  & {256{P2_EN[0]}};
229
    (P2IE  /2):   reg_dec  =  P2IE_D   & {256{P2_EN[0]}};
230
    (P2SEL /2):   reg_dec  =  P2SEL_D  & {256{P2_EN[0]}};
231
    (P3IN  /2):   reg_dec  =  P3IN_D   & {256{P3_EN[0]}};
232
    (P3OUT /2):   reg_dec  =  P3OUT_D  & {256{P3_EN[0]}};
233
    (P3DIR /2):   reg_dec  =  P3DIR_D  & {256{P3_EN[0]}};
234
    (P3SEL /2):   reg_dec  =  P3SEL_D  & {256{P3_EN[0]}};
235
    (P4IN  /2):   reg_dec  =  P4IN_D   & {256{P4_EN[0]}};
236
    (P4OUT /2):   reg_dec  =  P4OUT_D  & {256{P4_EN[0]}};
237
    (P4DIR /2):   reg_dec  =  P4DIR_D  & {256{P4_EN[0]}};
238
    (P4SEL /2):   reg_dec  =  P4SEL_D  & {256{P4_EN[0]}};
239
    (P5IN  /2):   reg_dec  =  P5IN_D   & {256{P5_EN[0]}};
240
    (P5OUT /2):   reg_dec  =  P5OUT_D  & {256{P5_EN[0]}};
241
    (P5DIR /2):   reg_dec  =  P5DIR_D  & {256{P5_EN[0]}};
242
    (P5SEL /2):   reg_dec  =  P5SEL_D  & {256{P5_EN[0]}};
243
    (P6IN  /2):   reg_dec  =  P6IN_D   & {256{P6_EN[0]}};
244
    (P6OUT /2):   reg_dec  =  P6OUT_D  & {256{P6_EN[0]}};
245
    (P6DIR /2):   reg_dec  =  P6DIR_D  & {256{P6_EN[0]}};
246
    (P6SEL /2):   reg_dec  =  P6SEL_D  & {256{P6_EN[0]}};
247
    default   :   reg_dec  =  {256{1'b0}};
248
  endcase
249
 
250
// Read/Write probes
251
wire         reg_lo_write =  per_wen[0] & per_en;
252
wire         reg_hi_write =  per_wen[1] & per_en;
253
wire         reg_read     = ~|per_wen   & per_en;
254
 
255
// Read/Write vectors
256
wire [255:0] reg_hi_wr    = reg_dec & {256{reg_hi_write}};
257
wire [255:0] reg_lo_wr    = reg_dec & {256{reg_lo_write}};
258
wire [255:0] reg_rd       = reg_dec & {256{reg_read}};
259
 
260
 
261
//============================================================================
262
// 3) REGISTERS
263
//============================================================================
264
 
265
// P1IN Register
266
//---------------
267 79 olivier.girard
reg  [7:0] p1in_s;
268 2 olivier.girard
reg  [7:0] p1in;
269
 
270
always @ (posedge mclk or posedge puc)
271 79 olivier.girard
  if (puc)
272
    begin
273
       p1in_s <=  8'h00;
274
       p1in   <=  8'h00;
275
    end
276
  else
277
    begin
278
       p1in_s <=  p1_din & P1_EN_MSK;
279
       p1in   <=  p1in_s & P1_EN_MSK;
280
    end
281 2 olivier.girard
 
282
 
283
// P1OUT Register
284
//----------------
285
reg  [7:0] p1out;
286
 
287
wire       p1out_wr  = P1OUT[0] ? reg_hi_wr[P1OUT/2] : reg_lo_wr[P1OUT/2];
288
wire [7:0] p1out_nxt = P1OUT[0] ? per_din[15:8]      : per_din[7:0];
289
 
290
always @ (posedge mclk or posedge puc)
291
  if (puc)            p1out <=  8'h00;
292
  else if (p1out_wr)  p1out <=  p1out_nxt & P1_EN_MSK;
293
 
294
assign p1_dout = p1out;
295
 
296
 
297
// P1DIR Register
298
//----------------
299
reg  [7:0] p1dir;
300
 
301
wire       p1dir_wr  = P1DIR[0] ? reg_hi_wr[P1DIR/2] : reg_lo_wr[P1DIR/2];
302
wire [7:0] p1dir_nxt = P1DIR[0] ? per_din[15:8]      : per_din[7:0];
303
 
304
always @ (posedge mclk or posedge puc)
305
  if (puc)            p1dir <=  8'h00;
306
  else if (p1dir_wr)  p1dir <=  p1dir_nxt & P1_EN_MSK;
307
 
308
assign p1_dout_en = p1dir;
309
 
310
 
311
// P1IFG Register
312
//----------------
313
reg  [7:0] p1ifg;
314
 
315
wire       p1ifg_wr  = P1IFG[0] ? reg_hi_wr[P1IFG/2] : reg_lo_wr[P1IFG/2];
316
wire [7:0] p1ifg_nxt = P1IFG[0] ? per_din[15:8]      : per_din[7:0];
317
wire [7:0] p1ifg_set;
318
 
319
always @ (posedge mclk or posedge puc)
320
  if (puc)            p1ifg <=  8'h00;
321
  else if (p1ifg_wr)  p1ifg <=  (p1ifg_nxt | p1ifg_set) & P1_EN_MSK;
322
  else                p1ifg <=  (p1ifg     | p1ifg_set) & P1_EN_MSK;
323
 
324
// P1IES Register
325
//----------------
326
reg  [7:0] p1ies;
327
 
328
wire       p1ies_wr  = P1IES[0] ? reg_hi_wr[P1IES/2] : reg_lo_wr[P1IES/2];
329
wire [7:0] p1ies_nxt = P1IES[0] ? per_din[15:8]      : per_din[7:0];
330
 
331
always @ (posedge mclk or posedge puc)
332
  if (puc)            p1ies <=  8'h00;
333
  else if (p1ies_wr)  p1ies <=  p1ies_nxt & P1_EN_MSK;
334
 
335
 
336
// P1IE Register
337
//----------------
338
reg  [7:0] p1ie;
339
 
340
wire       p1ie_wr  = P1IE[0] ? reg_hi_wr[P1IE/2] : reg_lo_wr[P1IE/2];
341
wire [7:0] p1ie_nxt = P1IE[0] ? per_din[15:8]     : per_din[7:0];
342
 
343
always @ (posedge mclk or posedge puc)
344
  if (puc)           p1ie <=  8'h00;
345
  else if (p1ie_wr)  p1ie <=  p1ie_nxt & P1_EN_MSK;
346
 
347
 
348
// P1SEL Register
349
//----------------
350
reg  [7:0] p1sel;
351
 
352
wire       p1sel_wr  = P1SEL[0] ? reg_hi_wr[P1SEL/2] : reg_lo_wr[P1SEL/2];
353
wire [7:0] p1sel_nxt = P1SEL[0] ? per_din[15:8]      : per_din[7:0];
354
 
355
always @ (posedge mclk or posedge puc)
356
  if (puc)           p1sel <=  8'h00;
357
  else if (p1sel_wr) p1sel <=  p1sel_nxt & P1_EN_MSK;
358
 
359
assign p1_sel = p1sel;
360
 
361
 
362
// P2IN Register
363
//---------------
364 79 olivier.girard
reg  [7:0] p2in_s;
365 2 olivier.girard
reg  [7:0] p2in;
366
 
367
always @ (posedge mclk or posedge puc)
368 79 olivier.girard
  if (puc)
369
    begin
370
       p2in_s <=  8'h00;
371
       p2in   <=  8'h00;
372
    end
373
  else
374
    begin
375
       p2in_s <=  p2_din & P2_EN_MSK;
376
       p2in   <=  p2in_s & P2_EN_MSK;
377
    end
378 2 olivier.girard
 
379
 
380
// P2OUT Register
381
//----------------
382
reg  [7:0] p2out;
383
 
384
wire       p2out_wr  = P2OUT[0] ? reg_hi_wr[P2OUT/2] : reg_lo_wr[P2OUT/2];
385
wire [7:0] p2out_nxt = P2OUT[0] ? per_din[15:8]      : per_din[7:0];
386
 
387
always @ (posedge mclk or posedge puc)
388
  if (puc)            p2out <=  8'h00;
389
  else if (p2out_wr)  p2out <=  p2out_nxt & P2_EN_MSK;
390
 
391
assign p2_dout = p2out;
392
 
393
 
394
// P2DIR Register
395
//----------------
396
reg  [7:0] p2dir;
397
 
398
wire       p2dir_wr  = P2DIR[0] ? reg_hi_wr[P2DIR/2] : reg_lo_wr[P2DIR/2];
399
wire [7:0] p2dir_nxt = P2DIR[0] ? per_din[15:8]      : per_din[7:0];
400
 
401
always @ (posedge mclk or posedge puc)
402
  if (puc)            p2dir <=  8'h00;
403
  else if (p2dir_wr)  p2dir <=  p2dir_nxt & P2_EN_MSK;
404
 
405
assign p2_dout_en = p2dir;
406
 
407
 
408
// P2IFG Register
409
//----------------
410
reg  [7:0] p2ifg;
411
 
412
wire       p2ifg_wr  = P2IFG[0] ? reg_hi_wr[P2IFG/2] : reg_lo_wr[P2IFG/2];
413
wire [7:0] p2ifg_nxt = P2IFG[0] ? per_din[15:8]      : per_din[7:0];
414
wire [7:0] p2ifg_set;
415
 
416
always @ (posedge mclk or posedge puc)
417
  if (puc)            p2ifg <=  8'h00;
418
  else if (p2ifg_wr)  p2ifg <=  (p2ifg_nxt | p2ifg_set) & P2_EN_MSK;
419
  else                p2ifg <=  (p2ifg     | p2ifg_set) & P2_EN_MSK;
420
 
421
 
422
// P2IES Register
423
//----------------
424
reg  [7:0] p2ies;
425
 
426
wire       p2ies_wr  = P2IES[0] ? reg_hi_wr[P2IES/2] : reg_lo_wr[P2IES/2];
427
wire [7:0] p2ies_nxt = P2IES[0] ? per_din[15:8]      : per_din[7:0];
428
 
429
always @ (posedge mclk or posedge puc)
430
  if (puc)            p2ies <=  8'h00;
431
  else if (p2ies_wr)  p2ies <=  p2ies_nxt & P2_EN_MSK;
432
 
433
 
434
// P2IE Register
435
//----------------
436
reg  [7:0] p2ie;
437
 
438
wire       p2ie_wr  = P2IE[0] ? reg_hi_wr[P2IE/2] : reg_lo_wr[P2IE/2];
439
wire [7:0] p2ie_nxt = P2IE[0] ? per_din[15:8]     : per_din[7:0];
440
 
441
always @ (posedge mclk or posedge puc)
442
  if (puc)           p2ie <=  8'h00;
443
  else if (p2ie_wr)  p2ie <=  p2ie_nxt & P2_EN_MSK;
444
 
445
 
446
// P2SEL Register
447
//----------------
448
reg  [7:0] p2sel;
449
 
450
wire       p2sel_wr  = P2SEL[0] ? reg_hi_wr[P2SEL/2] : reg_lo_wr[P2SEL/2];
451
wire [7:0] p2sel_nxt = P2SEL[0] ? per_din[15:8]      : per_din[7:0];
452
 
453
always @ (posedge mclk or posedge puc)
454
  if (puc)           p2sel <=  8'h00;
455
  else if (p2sel_wr) p2sel <=  p2sel_nxt & P2_EN_MSK;
456
 
457
assign p2_sel = p2sel;
458
 
459
 
460
// P3IN Register
461
//---------------
462 79 olivier.girard
reg  [7:0] p3in_s;
463 2 olivier.girard
reg  [7:0] p3in;
464
 
465
always @ (posedge mclk or posedge puc)
466 79 olivier.girard
  if (puc)
467
    begin
468
       p3in_s <=  8'h00;
469
       p3in   <=  8'h00;
470
    end
471
  else
472
    begin
473
       p3in_s <=  p3_din & P3_EN_MSK;
474
       p3in   <=  p3in_s & P3_EN_MSK;
475
    end
476 2 olivier.girard
 
477
 
478
// P3OUT Register
479
//----------------
480
reg  [7:0] p3out;
481
 
482
wire       p3out_wr  = P3OUT[0] ? reg_hi_wr[P3OUT/2] : reg_lo_wr[P3OUT/2];
483
wire [7:0] p3out_nxt = P3OUT[0] ? per_din[15:8]      : per_din[7:0];
484
 
485
always @ (posedge mclk or posedge puc)
486
  if (puc)            p3out <=  8'h00;
487
  else if (p3out_wr)  p3out <=  p3out_nxt & P3_EN_MSK;
488
 
489
assign p3_dout = p3out;
490
 
491
 
492
// P3DIR Register
493
//----------------
494
reg  [7:0] p3dir;
495
 
496
wire       p3dir_wr  = P3DIR[0] ? reg_hi_wr[P3DIR/2] : reg_lo_wr[P3DIR/2];
497
wire [7:0] p3dir_nxt = P3DIR[0] ? per_din[15:8]      : per_din[7:0];
498
 
499
always @ (posedge mclk or posedge puc)
500
  if (puc)            p3dir <=  8'h00;
501
  else if (p3dir_wr)  p3dir <=  p3dir_nxt & P3_EN_MSK;
502
 
503
assign p3_dout_en = p3dir;
504
 
505
 
506
// P3SEL Register
507
//----------------
508
reg  [7:0] p3sel;
509
 
510
wire       p3sel_wr  = P3SEL[0] ? reg_hi_wr[P3SEL/2] : reg_lo_wr[P3SEL/2];
511
wire [7:0] p3sel_nxt = P3SEL[0] ? per_din[15:8]      : per_din[7:0];
512
 
513
always @ (posedge mclk or posedge puc)
514
  if (puc)           p3sel <=  8'h00;
515
  else if (p3sel_wr) p3sel <=  p3sel_nxt & P3_EN_MSK;
516
 
517
assign p3_sel = p3sel;
518
 
519
 
520
// P4IN Register
521
//---------------
522 79 olivier.girard
reg  [7:0] p4in_s;
523 2 olivier.girard
reg  [7:0] p4in;
524
 
525
always @ (posedge mclk or posedge puc)
526 79 olivier.girard
  if (puc)
527
    begin
528
       p4in_s <=  8'h00;
529
       p4in   <=  8'h00;
530
    end
531
  else
532
    begin
533
       p4in_s <=  p4_din & P4_EN_MSK;
534
       p4in   <=  p4in_s & P4_EN_MSK;
535
    end
536 2 olivier.girard
 
537
 
538
// P4OUT Register
539
//----------------
540
reg  [7:0] p4out;
541
 
542
wire       p4out_wr  = P4OUT[0] ? reg_hi_wr[P4OUT/2] : reg_lo_wr[P4OUT/2];
543
wire [7:0] p4out_nxt = P4OUT[0] ? per_din[15:8]      : per_din[7:0];
544
 
545
always @ (posedge mclk or posedge puc)
546
  if (puc)            p4out <=  8'h00;
547
  else if (p4out_wr)  p4out <=  p4out_nxt & P4_EN_MSK;
548
 
549
assign p4_dout = p4out;
550
 
551
 
552
// P4DIR Register
553
//----------------
554
reg  [7:0] p4dir;
555
 
556
wire       p4dir_wr  = P4DIR[0] ? reg_hi_wr[P4DIR/2] : reg_lo_wr[P4DIR/2];
557
wire [7:0] p4dir_nxt = P4DIR[0] ? per_din[15:8]      : per_din[7:0];
558
 
559
always @ (posedge mclk or posedge puc)
560
  if (puc)            p4dir <=  8'h00;
561
  else if (p4dir_wr)  p4dir <=  p4dir_nxt & P4_EN_MSK;
562
 
563
assign p4_dout_en = p4dir;
564
 
565
 
566
// P4SEL Register
567
//----------------
568
reg  [7:0] p4sel;
569
 
570
wire       p4sel_wr  = P4SEL[0] ? reg_hi_wr[P4SEL/2] : reg_lo_wr[P4SEL/2];
571
wire [7:0] p4sel_nxt = P4SEL[0] ? per_din[15:8]      : per_din[7:0];
572
 
573
always @ (posedge mclk or posedge puc)
574
  if (puc)           p4sel <=  8'h00;
575
  else if (p4sel_wr) p4sel <=  p4sel_nxt & P4_EN_MSK;
576
 
577
assign p4_sel = p4sel;
578
 
579
 
580
// P5IN Register
581
//---------------
582 79 olivier.girard
reg  [7:0] p5in_s;
583 2 olivier.girard
reg  [7:0] p5in;
584
 
585
always @ (posedge mclk or posedge puc)
586 79 olivier.girard
  if (puc)
587
    begin
588
       p5in_s <=  8'h00;
589
       p5in   <=  8'h00;
590
    end
591
  else
592
    begin
593
       p5in_s <=  p5_din & P5_EN_MSK;
594
       p5in   <=  p5in_s & P5_EN_MSK;
595
    end
596 2 olivier.girard
 
597
 
598
// P5OUT Register
599
//----------------
600
reg  [7:0] p5out;
601
 
602
wire       p5out_wr  = P5OUT[0] ? reg_hi_wr[P5OUT/2] : reg_lo_wr[P5OUT/2];
603
wire [7:0] p5out_nxt = P5OUT[0] ? per_din[15:8]      : per_din[7:0];
604
 
605
always @ (posedge mclk or posedge puc)
606
  if (puc)            p5out <=  8'h00;
607
  else if (p5out_wr)  p5out <=  p5out_nxt & P5_EN_MSK;
608
 
609
assign p5_dout = p5out;
610
 
611
 
612
// P5DIR Register
613
//----------------
614
reg  [7:0] p5dir;
615
 
616
wire       p5dir_wr  = P5DIR[0] ? reg_hi_wr[P5DIR/2] : reg_lo_wr[P5DIR/2];
617
wire [7:0] p5dir_nxt = P5DIR[0] ? per_din[15:8]      : per_din[7:0];
618
 
619
always @ (posedge mclk or posedge puc)
620
  if (puc)            p5dir <=  8'h00;
621
  else if (p5dir_wr)  p5dir <=  p5dir_nxt & P5_EN_MSK;
622
 
623
assign p5_dout_en = p5dir;
624
 
625
 
626
// P5SEL Register
627
//----------------
628
reg  [7:0] p5sel;
629
 
630
wire       p5sel_wr  = P5SEL[0] ? reg_hi_wr[P5SEL/2] : reg_lo_wr[P5SEL/2];
631
wire [7:0] p5sel_nxt = P5SEL[0] ? per_din[15:8]      : per_din[7:0];
632
 
633
always @ (posedge mclk or posedge puc)
634
  if (puc)           p5sel <=  8'h00;
635
  else if (p5sel_wr) p5sel <=  p5sel_nxt & P5_EN_MSK;
636
 
637
assign p5_sel = p5sel;
638
 
639
 
640
// P6IN Register
641
//---------------
642 79 olivier.girard
reg  [7:0] p6in_s;
643 2 olivier.girard
reg  [7:0] p6in;
644
 
645
always @ (posedge mclk or posedge puc)
646 79 olivier.girard
  if (puc)
647
    begin
648
       p6in_s <=  8'h00;
649
       p6in   <=  8'h00;
650
    end
651
  else
652
    begin
653
       p6in_s <=  p6_din & P6_EN_MSK;
654
       p6in   <=  p6in_s & P6_EN_MSK;
655
    end
656 2 olivier.girard
 
657
 
658
// P6OUT Register
659
//----------------
660
reg  [7:0] p6out;
661
 
662
wire       p6out_wr  = P6OUT[0] ? reg_hi_wr[P6OUT/2] : reg_lo_wr[P6OUT/2];
663
wire [7:0] p6out_nxt = P6OUT[0] ? per_din[15:8]      : per_din[7:0];
664
 
665
always @ (posedge mclk or posedge puc)
666
  if (puc)            p6out <=  8'h00;
667
  else if (p6out_wr)  p6out <=  p6out_nxt & P6_EN_MSK;
668
 
669
assign p6_dout = p6out;
670
 
671
 
672
// P6DIR Register
673
//----------------
674
reg  [7:0] p6dir;
675
 
676
wire       p6dir_wr  = P6DIR[0] ? reg_hi_wr[P6DIR/2] : reg_lo_wr[P6DIR/2];
677
wire [7:0] p6dir_nxt = P6DIR[0] ? per_din[15:8]      : per_din[7:0];
678
 
679
always @ (posedge mclk or posedge puc)
680
  if (puc)            p6dir <=  8'h00;
681
  else if (p6dir_wr)  p6dir <=  p6dir_nxt & P6_EN_MSK;
682
 
683
assign p6_dout_en = p6dir;
684
 
685
 
686
// P6SEL Register
687
//----------------
688
reg  [7:0] p6sel;
689
 
690
wire       p6sel_wr  = P6SEL[0] ? reg_hi_wr[P6SEL/2] : reg_lo_wr[P6SEL/2];
691
wire [7:0] p6sel_nxt = P6SEL[0] ? per_din[15:8]      : per_din[7:0];
692
 
693
always @ (posedge mclk or posedge puc)
694
  if (puc)           p6sel <=  8'h00;
695
  else if (p6sel_wr) p6sel <=  p6sel_nxt & P6_EN_MSK;
696
 
697
assign p6_sel = p6sel;
698
 
699
 
700
 
701
//============================================================================
702
// 4) INTERRUPT GENERATION
703
//============================================================================
704
 
705
// Port 1 interrupt
706
//------------------
707
 
708
// Delay input
709
reg    [7:0] p1in_dly;
710
always @ (posedge mclk or posedge puc)
711
  if (puc)      p1in_dly <=  8'h00;
712
  else          p1in_dly <=  p1in & P1_EN_MSK;
713
 
714
// Edge detection
715
wire   [7:0] p1in_re   =   p1in & ~p1in_dly;
716
wire   [7:0] p1in_fe   =  ~p1in &  p1in_dly;
717
 
718
// Set interrupt flag
719
assign       p1ifg_set = {p1ies[7] ? p1in_fe[7] : p1in_re[7],
720
                          p1ies[6] ? p1in_fe[6] : p1in_re[6],
721
                          p1ies[5] ? p1in_fe[5] : p1in_re[5],
722
                          p1ies[4] ? p1in_fe[4] : p1in_re[4],
723
                          p1ies[3] ? p1in_fe[3] : p1in_re[3],
724
                          p1ies[2] ? p1in_fe[2] : p1in_re[2],
725
                          p1ies[1] ? p1in_fe[1] : p1in_re[1],
726
                          p1ies[0] ? p1in_fe[0] : p1in_re[0]} & P1_EN_MSK;
727
 
728
// Generate CPU interrupt
729
assign       irq_port1 = |(p1ie & p1ifg) & P1_EN[0];
730
 
731
 
732
// Port 1 interrupt
733
//------------------
734
 
735
// Delay input
736
reg    [7:0] p2in_dly;
737
always @ (posedge mclk or posedge puc)
738
  if (puc)      p2in_dly <=  8'h00;
739
  else          p2in_dly <=  p2in & P2_EN_MSK;
740
 
741
// Edge detection
742
wire   [7:0] p2in_re   =   p2in & ~p2in_dly;
743
wire   [7:0] p2in_fe   =  ~p2in &  p2in_dly;
744
 
745
// Set interrupt flag
746
assign       p2ifg_set = {p2ies[7] ? p2in_fe[7] : p2in_re[7],
747
                          p2ies[6] ? p2in_fe[6] : p2in_re[6],
748
                          p2ies[5] ? p2in_fe[5] : p2in_re[5],
749
                          p2ies[4] ? p2in_fe[4] : p2in_re[4],
750
                          p2ies[3] ? p2in_fe[3] : p2in_re[3],
751
                          p2ies[2] ? p2in_fe[2] : p2in_re[2],
752
                          p2ies[1] ? p2in_fe[1] : p2in_re[1],
753
                          p2ies[0] ? p2in_fe[0] : p2in_re[0]} & P2_EN_MSK;
754
 
755
// Generate CPU interrupt
756
assign      irq_port2 = |(p2ie & p2ifg) & P2_EN[0];
757
 
758
 
759
//============================================================================
760
// 5) DATA OUTPUT GENERATION
761
//============================================================================
762
 
763
// Data output mux
764
wire [15:0] p1in_rd   = (p1in  & {8{reg_rd[P1IN/2]}})  << (8 & {4{P1IN[0]}});
765
wire [15:0] p1out_rd  = (p1out & {8{reg_rd[P1OUT/2]}}) << (8 & {4{P1OUT[0]}});
766
wire [15:0] p1dir_rd  = (p1dir & {8{reg_rd[P1DIR/2]}}) << (8 & {4{P1DIR[0]}});
767
wire [15:0] p1ifg_rd  = (p1ifg & {8{reg_rd[P1IFG/2]}}) << (8 & {4{P1IFG[0]}});
768
wire [15:0] p1ies_rd  = (p1ies & {8{reg_rd[P1IES/2]}}) << (8 & {4{P1IES[0]}});
769
wire [15:0] p1ie_rd   = (p1ie  & {8{reg_rd[P1IE/2]}})  << (8 & {4{P1IE[0]}});
770
wire [15:0] p1sel_rd  = (p1sel & {8{reg_rd[P1SEL/2]}}) << (8 & {4{P1SEL[0]}});
771
wire [15:0] p2in_rd   = (p2in  & {8{reg_rd[P2IN/2]}})  << (8 & {4{P2IN[0]}});
772
wire [15:0] p2out_rd  = (p2out & {8{reg_rd[P2OUT/2]}}) << (8 & {4{P2OUT[0]}});
773
wire [15:0] p2dir_rd  = (p2dir & {8{reg_rd[P2DIR/2]}}) << (8 & {4{P2DIR[0]}});
774
wire [15:0] p2ifg_rd  = (p2ifg & {8{reg_rd[P2IFG/2]}}) << (8 & {4{P2IFG[0]}});
775
wire [15:0] p2ies_rd  = (p2ies & {8{reg_rd[P2IES/2]}}) << (8 & {4{P2IES[0]}});
776
wire [15:0] p2ie_rd   = (p2ie  & {8{reg_rd[P2IE/2]}})  << (8 & {4{P2IE[0]}});
777
wire [15:0] p2sel_rd  = (p2sel & {8{reg_rd[P2SEL/2]}}) << (8 & {4{P2SEL[0]}});
778
wire [15:0] p3in_rd   = (p3in  & {8{reg_rd[P3IN/2]}})  << (8 & {4{P3IN[0]}});
779
wire [15:0] p3out_rd  = (p3out & {8{reg_rd[P3OUT/2]}}) << (8 & {4{P3OUT[0]}});
780
wire [15:0] p3dir_rd  = (p3dir & {8{reg_rd[P3DIR/2]}}) << (8 & {4{P3DIR[0]}});
781
wire [15:0] p3sel_rd  = (p3sel & {8{reg_rd[P3SEL/2]}}) << (8 & {4{P3SEL[0]}});
782
wire [15:0] p4in_rd   = (p4in  & {8{reg_rd[P4IN/2]}})  << (8 & {4{P4IN[0]}});
783
wire [15:0] p4out_rd  = (p4out & {8{reg_rd[P4OUT/2]}}) << (8 & {4{P4OUT[0]}});
784
wire [15:0] p4dir_rd  = (p4dir & {8{reg_rd[P4DIR/2]}}) << (8 & {4{P4DIR[0]}});
785
wire [15:0] p4sel_rd  = (p4sel & {8{reg_rd[P4SEL/2]}}) << (8 & {4{P4SEL[0]}});
786
wire [15:0] p5in_rd   = (p5in  & {8{reg_rd[P5IN/2]}})  << (8 & {4{P5IN[0]}});
787
wire [15:0] p5out_rd  = (p5out & {8{reg_rd[P5OUT/2]}}) << (8 & {4{P5OUT[0]}});
788
wire [15:0] p5dir_rd  = (p5dir & {8{reg_rd[P5DIR/2]}}) << (8 & {4{P5DIR[0]}});
789
wire [15:0] p5sel_rd  = (p5sel & {8{reg_rd[P5SEL/2]}}) << (8 & {4{P5SEL[0]}});
790
wire [15:0] p6in_rd   = (p6in  & {8{reg_rd[P6IN/2]}})  << (8 & {4{P6IN[0]}});
791
wire [15:0] p6out_rd  = (p6out & {8{reg_rd[P6OUT/2]}}) << (8 & {4{P6OUT[0]}});
792
wire [15:0] p6dir_rd  = (p6dir & {8{reg_rd[P6DIR/2]}}) << (8 & {4{P6DIR[0]}});
793
wire [15:0] p6sel_rd  = (p6sel & {8{reg_rd[P6SEL/2]}}) << (8 & {4{P6SEL[0]}});
794
 
795
wire [15:0] per_dout  =  p1in_rd   |
796
                         p1out_rd  |
797
                         p1dir_rd  |
798
                         p1ifg_rd  |
799
                         p1ies_rd  |
800
                         p1ie_rd   |
801
                         p1sel_rd  |
802
                         p2in_rd   |
803
                         p2out_rd  |
804
                         p2dir_rd  |
805
                         p2ifg_rd  |
806
                         p2ies_rd  |
807
                         p2ie_rd   |
808
                         p2sel_rd  |
809
                         p3in_rd   |
810
                         p3out_rd  |
811
                         p3dir_rd  |
812
                         p3sel_rd  |
813
                         p4in_rd   |
814
                         p4out_rd  |
815
                         p4dir_rd  |
816
                         p4sel_rd  |
817
                         p5in_rd   |
818
                         p5out_rd  |
819
                         p5dir_rd  |
820
                         p5sel_rd  |
821
                         p6in_rd   |
822
                         p6out_rd  |
823
                         p6dir_rd  |
824
                         p6sel_rd;
825
 
826 34 olivier.girard
endmodule // omsp_gpio
827 2 olivier.girard
 
828 33 olivier.girard
`include "openMSP430_undefines.v"

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