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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_multiplier.v] - Blame information for rev 111

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1 71 olivier.girard
 
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//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: omsp_multiplier.v
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// 
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// *Module Description:
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//                       16x16 Hardware multiplier.
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 23 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
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//----------------------------------------------------------------------------
39 104 olivier.girard
`ifdef OMSP_NO_INCLUDE
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`else
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`include "openMSP430_defines.v"
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`endif
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module  omsp_multiplier (
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// OUTPUTs
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    per_dout,                       // Peripheral data output
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// INPUTs
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    mclk,                           // Main system clock
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    per_addr,                       // Peripheral address
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    per_din,                        // Peripheral data input
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    per_en,                         // Peripheral enable (high active)
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    per_we,                         // Peripheral write enable (high active)
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    puc_rst                         // Main system reset
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);
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// OUTPUTs
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//=========
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output       [15:0] per_dout;       // Peripheral data output
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// INPUTs
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//=========
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input               mclk;           // Main system clock
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input        [13:0] per_addr;       // Peripheral address
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input        [15:0] per_din;        // Peripheral data input
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input               per_en;         // Peripheral enable (high active)
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input         [1:0] per_we;         // Peripheral write enable (high active)
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input               puc_rst;        // Main system reset
70 71 olivier.girard
 
71
 
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//=============================================================================
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// 1)  PARAMETER/REGISTERS & WIRE DECLARATION
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//=============================================================================
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76 111 olivier.girard
// Register base address (must be aligned to decoder bit width)
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parameter       [14:0] BASE_ADDR   = 15'h0130;
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// Decoder bit width (defines how many bits are considered for address decoding)
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parameter              DEC_WD      =  4;
81 71 olivier.girard
 
82 111 olivier.girard
// Register addresses offset
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parameter [DEC_WD-1:0] OP1_MPY     = 'h0,
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                       OP1_MPYS    = 'h2,
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                       OP1_MAC     = 'h4,
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                       OP1_MACS    = 'h6,
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                       OP2         = 'h8,
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                       RESLO       = 'hA,
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                       RESHI       = 'hC,
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                       SUMEXT      = 'hE;
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92
// Register one-hot decoder utilities
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parameter              DEC_SZ      =  2**DEC_WD;
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parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
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96 71 olivier.girard
// Register one-hot decoder
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parameter [DEC_SZ-1:0] OP1_MPY_D   = (BASE_REG << OP1_MPY),
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                       OP1_MPYS_D  = (BASE_REG << OP1_MPYS),
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                       OP1_MAC_D   = (BASE_REG << OP1_MAC),
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                       OP1_MACS_D  = (BASE_REG << OP1_MACS),
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                       OP2_D       = (BASE_REG << OP2),
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                       RESLO_D     = (BASE_REG << RESLO),
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                       RESHI_D     = (BASE_REG << RESHI),
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                       SUMEXT_D    = (BASE_REG << SUMEXT);
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106
 
107
// Wire pre-declarations
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wire  result_wr;
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wire  result_clr;
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wire  early_read;
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112
 
113
//============================================================================
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// 2)  REGISTER DECODER
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//============================================================================
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// Local register selection
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wire              reg_sel   =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
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120
// Register local address
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wire [DEC_WD-1:0] reg_addr  =  {per_addr[DEC_WD-2:0], 1'b0};
122
 
123 71 olivier.girard
// Register address decode
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wire [DEC_SZ-1:0] reg_dec   =  (OP1_MPY_D   &  {DEC_SZ{(reg_addr == OP1_MPY  )}})  |
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                               (OP1_MPYS_D  &  {DEC_SZ{(reg_addr == OP1_MPYS )}})  |
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                               (OP1_MAC_D   &  {DEC_SZ{(reg_addr == OP1_MAC  )}})  |
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                               (OP1_MACS_D  &  {DEC_SZ{(reg_addr == OP1_MACS )}})  |
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                               (OP2_D       &  {DEC_SZ{(reg_addr == OP2      )}})  |
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                               (RESLO_D     &  {DEC_SZ{(reg_addr == RESLO    )}})  |
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                               (RESHI_D     &  {DEC_SZ{(reg_addr == RESHI    )}})  |
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                               (SUMEXT_D    &  {DEC_SZ{(reg_addr == SUMEXT   )}});
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133 71 olivier.girard
// Read/Write probes
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wire              reg_write =  |per_we & reg_sel;
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wire              reg_read  = ~|per_we & reg_sel;
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137
// Read/Write vectors
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wire [DEC_SZ-1:0] reg_wr    = reg_dec & {DEC_SZ{reg_write}};
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wire [DEC_SZ-1:0] reg_rd    = reg_dec & {DEC_SZ{reg_read}};
140 71 olivier.girard
 
141
 
142
//============================================================================
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// 3) REGISTERS
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//============================================================================
145
 
146
// OP1 Register
147
//-----------------   
148
reg  [15:0] op1;
149
 
150
wire        op1_wr = reg_wr[OP1_MPY]  |
151
                     reg_wr[OP1_MPYS] |
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                     reg_wr[OP1_MAC]  |
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                     reg_wr[OP1_MACS];
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155 111 olivier.girard
always @ (posedge mclk or posedge puc_rst)
156
  if (puc_rst)      op1 <=  16'h0000;
157 71 olivier.girard
  else if (op1_wr)  op1 <=  per_din;
158
 
159
wire [15:0] op1_rd  = op1;
160
 
161
 
162
// OP2 Register
163
//-----------------   
164
reg  [15:0] op2;
165
 
166
wire        op2_wr = reg_wr[OP2];
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168 111 olivier.girard
always @ (posedge mclk or posedge puc_rst)
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  if (puc_rst)      op2 <=  16'h0000;
170 71 olivier.girard
  else if (op2_wr)  op2 <=  per_din;
171
 
172
wire [15:0] op2_rd  = op2;
173
 
174
 
175
// RESLO Register
176
//-----------------   
177
reg  [15:0] reslo;
178
 
179
wire [15:0] reslo_nxt;
180
wire        reslo_wr = reg_wr[RESLO];
181
 
182 111 olivier.girard
always @ (posedge mclk or posedge puc_rst)
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  if (puc_rst)         reslo <=  16'h0000;
184 71 olivier.girard
  else if (reslo_wr)   reslo <=  per_din;
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  else if (result_clr) reslo <=  16'h0000;
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  else if (result_wr)  reslo <=  reslo_nxt;
187
 
188
wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo;
189
 
190
 
191
// RESHI Register
192
//-----------------   
193
reg  [15:0] reshi;
194
 
195
wire [15:0] reshi_nxt;
196
wire        reshi_wr = reg_wr[RESHI];
197
 
198 111 olivier.girard
always @ (posedge mclk or posedge puc_rst)
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  if (puc_rst)         reshi <=  16'h0000;
200 71 olivier.girard
  else if (reshi_wr)   reshi <=  per_din;
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  else if (result_clr) reshi <=  16'h0000;
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  else if (result_wr)  reshi <=  reshi_nxt;
203
 
204
wire [15:0] reshi_rd = early_read ? reshi_nxt  : reshi;
205
 
206
 
207
// SUMEXT Register
208
//-----------------   
209
reg  [1:0] sumext_s;
210
 
211
wire [1:0] sumext_s_nxt;
212
 
213 111 olivier.girard
always @ (posedge mclk or posedge puc_rst)
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  if (puc_rst)         sumext_s <=  2'b00;
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  else if (op2_wr)     sumext_s <=  2'b00;
216
  else if (result_wr)  sumext_s <=  sumext_s_nxt;
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wire [15:0] sumext_nxt = {{14{sumext_s_nxt[1]}}, sumext_s_nxt};
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wire [15:0] sumext     = {{14{sumext_s[1]}},     sumext_s};
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wire [15:0] sumext_rd  = early_read ? sumext_nxt : sumext;
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222
 
223
//============================================================================
224
// 4) DATA OUTPUT GENERATION
225
//============================================================================
226
 
227
// Data output mux
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wire [15:0] op1_mux    = op1_rd     & {16{reg_rd[OP1_MPY]  |
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                                          reg_rd[OP1_MPYS] |
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                                          reg_rd[OP1_MAC]  |
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                                          reg_rd[OP1_MACS]}};
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wire [15:0] op2_mux    = op2_rd     & {16{reg_rd[OP2]}};
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wire [15:0] reslo_mux  = reslo_rd   & {16{reg_rd[RESLO]}};
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wire [15:0] reshi_mux  = reshi_rd   & {16{reg_rd[RESHI]}};
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wire [15:0] sumext_mux = sumext_rd  & {16{reg_rd[SUMEXT]}};
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wire [15:0] per_dout   = op1_mux    |
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                         op2_mux    |
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                         reslo_mux  |
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                         reshi_mux  |
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                         sumext_mux;
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//============================================================================
245
// 5) HARDWARE MULTIPLIER FUNCTIONAL LOGIC
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//============================================================================
247
 
248
// Multiplier configuration
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//--------------------------
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251
// Detect signed mode
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reg sign_sel;
253 111 olivier.girard
always @ (posedge mclk or posedge puc_rst)
254
  if (puc_rst)     sign_sel <=  1'b0;
255 71 olivier.girard
  else if (op1_wr) sign_sel <=  reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
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257
 
258
// Detect accumulate mode
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reg acc_sel;
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always @ (posedge mclk or posedge puc_rst)
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  if (puc_rst)     acc_sel  <=  1'b0;
262 71 olivier.girard
  else if (op1_wr) acc_sel  <=  reg_wr[OP1_MAC]  | reg_wr[OP1_MACS];
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264
 
265
// Detect whenever the RESHI and RESLO registers should be cleared
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assign      result_clr = op2_wr & ~acc_sel;
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268
// Combine RESHI & RESLO 
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wire [31:0] result     = {reshi, reslo};
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// 16x16 Multiplier (result computed in 1 clock cycle)
273
//-----------------------------------------------------
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`ifdef MPY_16x16
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// Detect start of a multiplication
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reg cycle;
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always @ (posedge mclk or posedge puc_rst)
279
  if (puc_rst) cycle <=  1'b0;
280
  else         cycle <=  op2_wr;
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282
assign result_wr = cycle;
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// Expand the operands to support signed & unsigned operations
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wire signed [16:0] op1_xp = {sign_sel & op1[15], op1};
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wire signed [16:0] op2_xp = {sign_sel & op2[15], op2};
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288
 
289
// 17x17 signed multiplication
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wire signed [33:0] product = op1_xp * op2_xp;
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292
// Accumulate
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wire [32:0] result_nxt = {1'b0, result} + {1'b0, product[31:0]};
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295
 
296
// Next register values
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assign reslo_nxt    = result_nxt[15:0];
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assign reshi_nxt    = result_nxt[31:16];
299
assign sumext_s_nxt =  sign_sel ? {2{result_nxt[31]}} :
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                                  {1'b0, result_nxt[32]};
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302
 
303
// Since the MAC is completed within 1 clock cycle,
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// an early read can't happen.
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assign early_read   = 1'b0;
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308
// 16x8 Multiplier (result computed in 2 clock cycles)
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//-----------------------------------------------------
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`else
311
 
312
// Detect start of a multiplication
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reg [1:0] cycle;
314 111 olivier.girard
always @ (posedge mclk or posedge puc_rst)
315
  if (puc_rst) cycle <=  2'b00;
316
  else         cycle <=  {cycle[0], op2_wr};
317 71 olivier.girard
 
318
assign result_wr = |cycle;
319
 
320
 
321
// Expand the operands to support signed & unsigned operations
322
wire signed [16:0] op1_xp    = {sign_sel & op1[15], op1};
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wire signed  [8:0] op2_hi_xp = {sign_sel & op2[15], op2[15:8]};
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wire signed  [8:0] op2_lo_xp = {              1'b0, op2[7:0]};
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wire signed  [8:0] op2_xp    = cycle[0] ? op2_hi_xp : op2_lo_xp;
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327
 
328
// 17x9 signed multiplication
329
wire signed [25:0] product    = op1_xp * op2_xp;
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331
wire        [31:0] product_xp = cycle[0] ? {product[23:0], 8'h00} :
332
                                           {{8{sign_sel & product[23]}}, product[23:0]};
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334
// Accumulate
335
wire [32:0] result_nxt  = {1'b0, result} + {1'b0, product_xp[31:0]};
336
 
337
 
338
// Next register values
339
assign reslo_nxt    = result_nxt[15:0];
340
assign reshi_nxt    = result_nxt[31:16];
341
assign sumext_s_nxt =  sign_sel ? {2{result_nxt[31]}} :
342
                                  {1'b0, result_nxt[32] | sumext_s[0]};
343
 
344
// Since the MAC is completed within 2 clock cycle,
345
// an early read can happen during the second cycle.
346
assign early_read   = cycle[1];
347
 
348
`endif
349
 
350
 
351
endmodule // omsp_multiplier
352
 
353 104 olivier.girard
`ifdef OMSP_NO_INCLUDE
354
`else
355 71 olivier.girard
`include "openMSP430_undefines.v"
356 104 olivier.girard
`endif

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