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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Blame information for rev 111

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1 80 olivier.girard
//----------------------------------------------------------------------------
2
// Copyright (C) 2001 Authors
3
//
4
// This source file may be used and distributed without restriction provided
5
// that this copyright statement is not removed from the file and that any
6
// derivative work contains the original copyright notice and the associated
7
// disclaimer.
8
//
9
// This source file is free software; you can redistribute it and/or modify
10
// it under the terms of the GNU Lesser General Public License as published
11
// by the Free Software Foundation; either version 2.1 of the License, or
12
// (at your option) any later version.
13
//
14
// This source is distributed in the hope that it will be useful, but WITHOUT
15
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
17
// License for more details.
18
//
19
// You should have received a copy of the GNU Lesser General Public License
20
// along with this source; if not, write to the Free Software Foundation,
21
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
22
//
23
//----------------------------------------------------------------------------
24
//
25
// *File Name: openMSP430.v
26
// 
27
// *Module Description:
28
//                       openMSP430 Top level file
29
//
30
// *Author(s):
31
//              - Olivier Girard,    olgirard@gmail.com
32
//
33
//----------------------------------------------------------------------------
34 111 olivier.girard
// $Rev: 103 $
35 80 olivier.girard
// $LastChangedBy: olivier.girard $
36 111 olivier.girard
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
37 80 olivier.girard
//----------------------------------------------------------------------------
38 104 olivier.girard
`ifdef OMSP_NO_INCLUDE
39
`else
40 80 olivier.girard
`include "openMSP430_defines.v"
41 104 olivier.girard
`endif
42 80 olivier.girard
 
43
module  openMSP430 (
44
 
45
// OUTPUTs
46
    aclk_en,                       // ACLK enable
47
    dbg_freeze,                    // Freeze peripherals
48
    dbg_uart_txd,                  // Debug interface: UART TXD
49
    dmem_addr,                     // Data Memory address
50
    dmem_cen,                      // Data Memory chip enable (low active)
51
    dmem_din,                      // Data Memory data input
52
    dmem_wen,                      // Data Memory write enable (low active)
53
    irq_acc,                       // Interrupt request accepted (one-hot signal)
54
    mclk,                          // Main system clock
55
    per_addr,                      // Peripheral address
56
    per_din,                       // Peripheral data input
57 107 olivier.girard
    per_we,                        // Peripheral write enable (high active)
58 80 olivier.girard
    per_en,                        // Peripheral enable (high active)
59
    pmem_addr,                     // Program Memory address
60
    pmem_cen,                      // Program Memory chip enable (low active)
61
    pmem_din,                      // Program Memory data input (optional)
62
    pmem_wen,                      // Program Memory write enable (low active) (optional)
63 111 olivier.girard
    puc_rst,                       // Main system reset
64 80 olivier.girard
    smclk_en,                      // SMCLK enable
65
 
66
// INPUTs
67 107 olivier.girard
    cpu_en,                        // Enable CPU code execution (asynchronous)
68
    dbg_en,                        // Debug interface enable (asynchronous)
69
    dbg_uart_rxd,                  // Debug interface: UART RXD (asynchronous)
70 80 olivier.girard
    dco_clk,                       // Fast oscillator (fast clock)
71
    dmem_dout,                     // Data Memory data output
72
    irq,                           // Maskable interrupts
73
    lfxt_clk,                      // Low frequency oscillator (typ 32kHz)
74
    nmi,                           // Non-maskable interrupt (asynchronous)
75
    per_dout,                      // Peripheral data output
76
    pmem_dout,                     // Program Memory data output
77 107 olivier.girard
    reset_n                        // Reset Pin (low active, asynchronous)
78 80 olivier.girard
);
79
 
80
// OUTPUTs
81
//=========
82
output               aclk_en;      // ACLK enable
83
output               dbg_freeze;   // Freeze peripherals
84
output               dbg_uart_txd; // Debug interface: UART TXD
85
output [`DMEM_MSB:0] dmem_addr;    // Data Memory address
86
output               dmem_cen;     // Data Memory chip enable (low active)
87
output        [15:0] dmem_din;     // Data Memory data input
88
output         [1:0] dmem_wen;     // Data Memory write enable (low active)
89
output        [13:0] irq_acc;      // Interrupt request accepted (one-hot signal)
90
output               mclk;         // Main system clock
91 111 olivier.girard
output        [13:0] per_addr;     // Peripheral address
92 80 olivier.girard
output        [15:0] per_din;      // Peripheral data input
93 107 olivier.girard
output         [1:0] per_we;       // Peripheral write enable (high active)
94 80 olivier.girard
output               per_en;       // Peripheral enable (high active)
95
output [`PMEM_MSB:0] pmem_addr;    // Program Memory address
96
output               pmem_cen;     // Program Memory chip enable (low active)
97
output        [15:0] pmem_din;     // Program Memory data input (optional)
98
output         [1:0] pmem_wen;     // Program Memory write enable (low active) (optional)
99 111 olivier.girard
output               puc_rst;      // Main system reset
100 80 olivier.girard
output               smclk_en;     // SMCLK enable
101
 
102
 
103
// INPUTs
104
//=========
105 107 olivier.girard
input                cpu_en;       // Enable CPU code execution (asynchronous)
106
input                dbg_en;       // Debug interface enable (asynchronous)
107
input                dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
108 80 olivier.girard
input                dco_clk;      // Fast oscillator (fast clock)
109
input         [15:0] dmem_dout;    // Data Memory data output
110
input         [13:0] irq;          // Maskable interrupts
111
input                lfxt_clk;     // Low frequency oscillator (typ 32kHz)
112
input                nmi;          // Non-maskable interrupt (asynchronous)
113
input         [15:0] per_dout;     // Peripheral data output
114
input         [15:0] pmem_dout;    // Program Memory data output
115 107 olivier.girard
input                reset_n;      // Reset Pin (active low, asynchronous)
116 80 olivier.girard
 
117
 
118
 
119
//=============================================================================
120
// 1)  INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
121
//=============================================================================
122
 
123
wire          [7:0] inst_ad;
124
wire          [7:0] inst_as;
125
wire         [11:0] inst_alu;
126
wire                inst_bw;
127 111 olivier.girard
wire                inst_irq_rst;
128
wire                inst_mov;
129 80 olivier.girard
wire         [15:0] inst_dest;
130
wire         [15:0] inst_dext;
131
wire         [15:0] inst_sext;
132
wire          [7:0] inst_so;
133
wire         [15:0] inst_src;
134
wire          [2:0] inst_type;
135 111 olivier.girard
wire          [7:0] inst_jmp;
136 80 olivier.girard
wire          [3:0] e_state;
137
wire                exec_done;
138 111 olivier.girard
wire                decode_noirq;
139
wire                cpu_en_s;
140
wire                cpuoff;
141
wire                oscoff;
142
wire                scg1;
143
wire                por;
144
wire                gie;
145 80 olivier.girard
 
146
wire         [15:0] eu_mab;
147
wire         [15:0] eu_mdb_in;
148
wire         [15:0] eu_mdb_out;
149
wire          [1:0] eu_mb_wr;
150 111 olivier.girard
wire                eu_mb_en;
151 80 olivier.girard
wire         [15:0] fe_mab;
152
wire         [15:0] fe_mdb_in;
153 111 olivier.girard
wire                fe_mb_en;
154
wire                fe_pmem_wait;
155 80 olivier.girard
 
156 111 olivier.girard
wire                pc_sw_wr;
157 80 olivier.girard
wire         [15:0] pc_sw;
158
wire         [15:0] pc;
159
wire         [15:0] pc_nxt;
160
 
161 111 olivier.girard
wire                nmie;
162
wire                nmi_acc;
163
wire                nmi_evt;
164
 
165
wire                wdtie;
166
wire                wdtifg_set;
167
wire                wdtpw_error;
168
wire                wdttmsel;
169
wire                wdt_irq;
170
wire                wdt_reset;
171
 
172
wire                dbg_clk;
173
wire                dbg_rst;
174
wire                dbg_en_s;
175
wire                dbg_halt_st;
176 86 olivier.girard
wire                dbg_halt_cmd;
177
wire                dbg_mem_en;
178
wire                dbg_reg_wr;
179 107 olivier.girard
wire                dbg_cpu_reset;
180 80 olivier.girard
wire         [15:0] dbg_mem_addr;
181
wire         [15:0] dbg_mem_dout;
182
wire         [15:0] dbg_mem_din;
183
wire         [15:0] dbg_reg_din;
184
wire          [1:0] dbg_mem_wr;
185
 
186
wire         [15:0] per_dout_or;
187
wire         [15:0] per_dout_sfr;
188
wire         [15:0] per_dout_wdog;
189
wire         [15:0] per_dout_mpy;
190
wire         [15:0] per_dout_clk;
191
 
192
 
193
//=============================================================================
194
// 2)  GLOBAL CLOCK & RESET MANAGEMENT
195
//=============================================================================
196
 
197
omsp_clock_module clock_module_0 (
198
 
199
// OUTPUTs
200
    .aclk_en      (aclk_en),       // ACLK enablex
201 107 olivier.girard
    .cpu_en_s     (cpu_en_s),      // Enable CPU code execution (synchronous)
202
    .dbg_clk      (dbg_clk),       // Debug unit clock
203
    .dbg_en_s     (dbg_en_s),      // Debug interface enable (synchronous)
204
    .dbg_rst      (dbg_rst),       // Debug unit reset
205 80 olivier.girard
    .mclk         (mclk),          // Main system clock
206
    .per_dout     (per_dout_clk),  // Peripheral data output
207
    .por          (por),           // Power-on reset
208 111 olivier.girard
    .puc_rst      (puc_rst),       // Main system reset
209 80 olivier.girard
    .smclk_en     (smclk_en),      // SMCLK enable
210
 
211
// INPUTs
212 107 olivier.girard
    .cpu_en       (cpu_en),        // Enable CPU code execution (asynchronous)
213
    .dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
214
    .dbg_en       (dbg_en),        // Debug interface enable (asynchronous)
215 80 olivier.girard
    .dco_clk      (dco_clk),       // Fast oscillator (fast clock)
216
    .lfxt_clk     (lfxt_clk),      // Low frequency oscillator (typ 32kHz)
217
    .oscoff       (oscoff),        // Turns off LFXT1 clock input
218
    .per_addr     (per_addr),      // Peripheral address
219
    .per_din      (per_din),       // Peripheral data input
220
    .per_en       (per_en),        // Peripheral enable (high active)
221 107 olivier.girard
    .per_we       (per_we),        // Peripheral write enable (high active)
222
    .reset_n      (reset_n),       // Reset Pin (low active, asynchronous)
223 80 olivier.girard
    .scg1         (scg1),          // System clock generator 1. Turns off the SMCLK
224
    .wdt_reset    (wdt_reset)      // Watchdog-timer reset
225
);
226
 
227
 
228
//=============================================================================
229
// 3)  FRONTEND (<=> FETCH & DECODE)
230
//=============================================================================
231
 
232
omsp_frontend frontend_0 (
233
 
234
// OUTPUTs
235
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
236
    .decode_noirq (decode_noirq),  // Frontend decode instruction
237
    .e_state      (e_state),       // Execution state
238
    .exec_done    (exec_done),     // Execution completed
239
    .inst_ad      (inst_ad),       // Decoded Inst: destination addressing mode
240
    .inst_as      (inst_as),       // Decoded Inst: source addressing mode
241
    .inst_alu     (inst_alu),      // ALU control signals
242
    .inst_bw      (inst_bw),       // Decoded Inst: byte width
243
    .inst_dest    (inst_dest),     // Decoded Inst: destination (one hot)
244
    .inst_dext    (inst_dext),     // Decoded Inst: destination extended instruction word
245
    .inst_irq_rst (inst_irq_rst),  // Decoded Inst: Reset interrupt
246
    .inst_jmp     (inst_jmp),      // Decoded Inst: Conditional jump
247 105 olivier.girard
    .inst_mov     (inst_mov),      // Decoded Inst: mov instruction
248 80 olivier.girard
    .inst_sext    (inst_sext),     // Decoded Inst: source extended instruction word
249
    .inst_so      (inst_so),       // Decoded Inst: Single-operand arithmetic
250
    .inst_src     (inst_src),      // Decoded Inst: source (one hot)
251
    .inst_type    (inst_type),     // Decoded Instruction type
252
    .irq_acc      (irq_acc),       // Interrupt request accepted
253
    .mab          (fe_mab),        // Frontend Memory address bus
254
    .mb_en        (fe_mb_en),      // Frontend Memory bus enable
255
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
256
    .pc           (pc),            // Program counter
257
    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
258
 
259
// INPUTs
260 107 olivier.girard
    .cpu_en_s     (cpu_en_s),      // Enable CPU code execution (synchronous)
261 80 olivier.girard
    .cpuoff       (cpuoff),        // Turns off the CPU
262
    .dbg_halt_cmd (dbg_halt_cmd),  // Halt CPU command
263
    .dbg_reg_sel  (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
264
    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
265
    .gie          (gie),           // General interrupt enable
266
    .irq          (irq),           // Maskable interrupts
267
    .mclk         (mclk),          // Main system clock
268
    .mdb_in       (fe_mdb_in),     // Frontend Memory data bus input
269
    .nmi_evt      (nmi_evt),       // Non-maskable interrupt event
270
    .pc_sw        (pc_sw),         // Program counter software value
271
    .pc_sw_wr     (pc_sw_wr),      // Program counter software write
272 111 olivier.girard
    .puc_rst      (puc_rst),       // Main system reset
273 80 olivier.girard
    .wdt_irq      (wdt_irq)        // Watchdog-timer interrupt
274
);
275
 
276
 
277
//=============================================================================
278
// 4)  EXECUTION UNIT
279
//=============================================================================
280
 
281
omsp_execution_unit execution_unit_0 (
282
 
283
// OUTPUTs
284
    .cpuoff       (cpuoff),        // Turns off the CPU
285
    .dbg_reg_din  (dbg_reg_din),   // Debug unit CPU register data input
286
    .mab          (eu_mab),        // Memory address bus
287
    .mb_en        (eu_mb_en),      // Memory bus enable
288
    .mb_wr        (eu_mb_wr),      // Memory bus write transfer
289
    .mdb_out      (eu_mdb_out),    // Memory data bus output
290
    .oscoff       (oscoff),        // Turns off LFXT1 clock input
291
    .pc_sw        (pc_sw),         // Program counter software value
292
    .pc_sw_wr     (pc_sw_wr),      // Program counter software write
293
    .scg1         (scg1),          // System clock generator 1. Turns off the SMCLK
294
 
295
// INPUTs
296
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
297
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
298
    .dbg_reg_wr   (dbg_reg_wr),    // Debug unit CPU register write
299
    .e_state      (e_state),       // Execution state
300
    .exec_done    (exec_done),     // Execution completed
301
    .gie          (gie),           // General interrupt enable
302
    .inst_ad      (inst_ad),       // Decoded Inst: destination addressing mode
303
    .inst_as      (inst_as),       // Decoded Inst: source addressing mode
304
    .inst_alu     (inst_alu),      // ALU control signals
305
    .inst_bw      (inst_bw),       // Decoded Inst: byte width
306
    .inst_dest    (inst_dest),     // Decoded Inst: destination (one hot)
307
    .inst_dext    (inst_dext),     // Decoded Inst: destination extended instruction word
308
    .inst_irq_rst (inst_irq_rst),  // Decoded Inst: reset interrupt
309
    .inst_jmp     (inst_jmp),      // Decoded Inst: Conditional jump
310 105 olivier.girard
    .inst_mov     (inst_mov),      // Decoded Inst: mov instruction
311 80 olivier.girard
    .inst_sext    (inst_sext),     // Decoded Inst: source extended instruction word
312
    .inst_so      (inst_so),       // Decoded Inst: Single-operand arithmetic
313
    .inst_src     (inst_src),      // Decoded Inst: source (one hot)
314
    .inst_type    (inst_type),     // Decoded Instruction type
315
    .mclk         (mclk),          // Main system clock
316
    .mdb_in       (eu_mdb_in),     // Memory data bus input
317
    .pc           (pc),            // Program counter
318
    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
319 111 olivier.girard
    .puc_rst      (puc_rst)        // Main system reset
320 80 olivier.girard
);
321
 
322
 
323
//=============================================================================
324
// 5)  MEMORY BACKBONE
325
//=============================================================================
326
 
327
omsp_mem_backbone mem_backbone_0 (
328
 
329
// OUTPUTs
330
    .dbg_mem_din  (dbg_mem_din),   // Debug unit Memory data input
331
    .dmem_addr    (dmem_addr),     // Data Memory address
332
    .dmem_cen     (dmem_cen),      // Data Memory chip enable (low active)
333
    .dmem_din     (dmem_din),      // Data Memory data input
334
    .dmem_wen     (dmem_wen),      // Data Memory write enable (low active)
335
    .eu_mdb_in    (eu_mdb_in),     // Execution Unit Memory data bus input
336
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
337
    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
338
    .per_addr     (per_addr),      // Peripheral address
339
    .per_din      (per_din),       // Peripheral data input
340 107 olivier.girard
    .per_we       (per_we),        // Peripheral write enable (high active)
341 80 olivier.girard
    .per_en       (per_en),        // Peripheral enable (high active)
342
    .pmem_addr    (pmem_addr),     // Program Memory address
343
    .pmem_cen     (pmem_cen),      // Program Memory chip enable (low active)
344
    .pmem_din     (pmem_din),      // Program Memory data input (optional)
345
    .pmem_wen     (pmem_wen),      // Program Memory write enable (low active) (optional)
346
 
347
// INPUTs
348
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
349
    .dbg_mem_addr (dbg_mem_addr),  // Debug address for rd/wr access
350
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
351
    .dbg_mem_en   (dbg_mem_en),    // Debug unit memory enable
352
    .dbg_mem_wr   (dbg_mem_wr),    // Debug unit memory write
353
    .dmem_dout    (dmem_dout),     // Data Memory data output
354
    .eu_mab       (eu_mab[15:1]),  // Execution Unit Memory address bus
355
    .eu_mb_en     (eu_mb_en),      // Execution Unit Memory bus enable
356
    .eu_mb_wr     (eu_mb_wr),      // Execution Unit Memory bus write transfer
357
    .eu_mdb_out   (eu_mdb_out),    // Execution Unit Memory data bus output
358
    .fe_mab       (fe_mab[15:1]),  // Frontend Memory address bus
359
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
360
    .mclk         (mclk),          // Main system clock
361
    .per_dout     (per_dout_or),   // Peripheral data output
362
    .pmem_dout    (pmem_dout),     // Program Memory data output
363 111 olivier.girard
    .puc_rst      (puc_rst)        // Main system reset
364 80 olivier.girard
);
365
 
366
 
367
//=============================================================================
368
// 6)  SPECIAL FUNCTION REGISTERS
369
//=============================================================================
370
 
371
omsp_sfr sfr_0 (
372
 
373
// OUTPUTs
374
    .nmie         (nmie),          // Non-maskable interrupt enable
375
    .per_dout     (per_dout_sfr),  // Peripheral data output
376
    .wdt_irq      (wdt_irq),       // Watchdog-timer interrupt
377
    .wdt_reset    (wdt_reset),     // Watchdog-timer reset
378
    .wdtie        (wdtie),         // Watchdog-timer interrupt enable
379
 
380
// INPUTs
381
    .mclk         (mclk),          // Main system clock
382
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
383
    .per_addr     (per_addr),      // Peripheral address
384
    .per_din      (per_din),       // Peripheral data input
385
    .per_en       (per_en),        // Peripheral enable (high active)
386 107 olivier.girard
    .per_we       (per_we),        // Peripheral write enable (high active)
387 80 olivier.girard
    .por          (por),           // Power-on reset
388 111 olivier.girard
    .puc_rst      (puc_rst),       // Main system reset
389 80 olivier.girard
    .wdtifg_clr   (irq_acc[10]),   // Clear Watchdog-timer interrupt flag
390
    .wdtifg_set   (wdtifg_set),    // Set Watchdog-timer interrupt flag
391
    .wdtpw_error  (wdtpw_error),   // Watchdog-timer password error
392
    .wdttmsel     (wdttmsel)       // Watchdog-timer mode select
393
);
394
 
395
 
396
//=============================================================================
397
// 7)  WATCHDOG TIMER
398
//=============================================================================
399
 
400
omsp_watchdog watchdog_0 (
401
 
402
// OUTPUTs
403
    .nmi_evt      (nmi_evt),       // NMI Event
404
    .per_dout     (per_dout_wdog), // Peripheral data output
405
    .wdtifg_set   (wdtifg_set),    // Set Watchdog-timer interrupt flag
406
    .wdtpw_error  (wdtpw_error),   // Watchdog-timer password error
407
    .wdttmsel     (wdttmsel),      // Watchdog-timer mode select
408
 
409
// INPUTs
410
    .aclk_en      (aclk_en),       // ACLK enable
411
    .dbg_freeze   (dbg_freeze),    // Freeze Watchdog counter
412
    .mclk         (mclk),          // Main system clock
413
    .nmi          (nmi),           // Non-maskable interrupt (asynchronous)
414
    .nmie         (nmie),          // Non-maskable interrupt enable
415
    .per_addr     (per_addr),      // Peripheral address
416
    .per_din      (per_din),       // Peripheral data input
417
    .per_en       (per_en),        // Peripheral enable (high active)
418 107 olivier.girard
    .per_we       (per_we),        // Peripheral write enable (high active)
419 111 olivier.girard
    .puc_rst      (puc_rst),       // Main system reset
420 80 olivier.girard
    .smclk_en     (smclk_en),      // SMCLK enable
421
    .wdtie        (wdtie)          // Watchdog-timer interrupt enable
422
);
423
 
424
 
425
//=============================================================================
426
// 8)  HARDWARE MULTIPLIER
427
//=============================================================================
428
`ifdef MULTIPLIER
429
omsp_multiplier multiplier_0 (
430
 
431
// OUTPUTs
432
    .per_dout     (per_dout_mpy),  // Peripheral data output
433
 
434
// INPUTs
435
    .mclk         (mclk),          // Main system clock
436
    .per_addr     (per_addr),      // Peripheral address
437
    .per_din      (per_din),       // Peripheral data input
438
    .per_en       (per_en),        // Peripheral enable (high active)
439 107 olivier.girard
    .per_we       (per_we),        // Peripheral write enable (high active)
440 111 olivier.girard
    .puc_rst      (puc_rst)        // Main system reset
441 80 olivier.girard
);
442
`else
443
assign per_dout_mpy = 16'h0000;
444
`endif
445
 
446
//=============================================================================
447
// 9)  PERIPHERALS' OUTPUT BUS
448
//=============================================================================
449
 
450
assign  per_dout_or  =  per_dout      |
451
                        per_dout_clk  |
452
                        per_dout_sfr  |
453
                        per_dout_wdog |
454
                        per_dout_mpy;
455
 
456
 
457
//=============================================================================
458
// 10)  DEBUG INTERFACE
459
//=============================================================================
460
 
461
`ifdef DBG_EN
462
omsp_dbg dbg_0 (
463
 
464
// OUTPUTs
465
    .dbg_freeze   (dbg_freeze),    // Freeze peripherals
466
    .dbg_halt_cmd (dbg_halt_cmd),  // Halt CPU command
467
    .dbg_mem_addr (dbg_mem_addr),  // Debug address for rd/wr access
468
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
469
    .dbg_mem_en   (dbg_mem_en),    // Debug unit memory enable
470
    .dbg_mem_wr   (dbg_mem_wr),    // Debug unit memory write
471
    .dbg_reg_wr   (dbg_reg_wr),    // Debug unit CPU register write
472 107 olivier.girard
    .dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
473 80 olivier.girard
    .dbg_uart_txd (dbg_uart_txd),  // Debug interface: UART TXD
474
 
475
// INPUTs
476 107 olivier.girard
    .cpu_en_s     (cpu_en_s),      // Enable CPU code execution (synchronous)
477
    .dbg_clk      (dbg_clk),       // Debug unit clock
478
    .dbg_en_s     (dbg_en_s),      // Debug interface enable (synchronous)
479 80 olivier.girard
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
480
    .dbg_mem_din  (dbg_mem_din),   // Debug unit Memory data input
481
    .dbg_reg_din  (dbg_reg_din),   // Debug unit CPU register data input
482 107 olivier.girard
    .dbg_rst      (dbg_rst),       // Debug unit reset
483
    .dbg_uart_rxd (dbg_uart_rxd),  // Debug interface: UART RXD (asynchronous)
484 80 olivier.girard
    .decode_noirq (decode_noirq),  // Frontend decode instruction
485
    .eu_mab       (eu_mab),        // Execution-Unit Memory address bus
486
    .eu_mb_en     (eu_mb_en),      // Execution-Unit Memory bus enable
487
    .eu_mb_wr     (eu_mb_wr),      // Execution-Unit Memory bus write transfer
488
    .eu_mdb_in    (eu_mdb_in),     // Memory data bus input
489
    .eu_mdb_out   (eu_mdb_out),    // Memory data bus output
490
    .exec_done    (exec_done),     // Execution completed
491
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
492
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
493
    .pc           (pc),            // Program counter
494 111 olivier.girard
    .puc_rst      (puc_rst)        // Main system reset
495 80 olivier.girard
);
496
 
497
`else
498 107 olivier.girard
assign dbg_freeze    =  ~cpu_en_s;
499
assign dbg_halt_cmd  =  1'b0;
500
assign dbg_mem_addr  = 16'h0000;
501
assign dbg_mem_dout  = 16'h0000;
502
assign dbg_mem_en    =  1'b0;
503
assign dbg_mem_wr    =  2'b00;
504
assign dbg_reg_wr    =  1'b0;
505
assign dbg_cpu_reset =  1'b0;
506
assign dbg_uart_txd  =  1'b0;
507 80 olivier.girard
`endif
508
 
509
 
510
endmodule // openMSP430
511
 
512 104 olivier.girard
`ifdef OMSP_NO_INCLUDE
513
`else
514 80 olivier.girard
`include "openMSP430_undefines.v"
515 104 olivier.girard
`endif

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