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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [template_periph_16b.s43] - Blame information for rev 2

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1 2 olivier.girard
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                    16 BIT PERIPHERAL TEMPLATE                             */
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/*---------------------------------------------------------------------------*/
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/* Test the 16 bit peripheral template:                                      */
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/*                                     - Read/Write register access.         */
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/*===========================================================================*/
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.global main
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.set   CNTRL1, 0x0190
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.set   CNTRL2, 0x0192
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.set   CNTRL3, 0x0194
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.set   CNTRL4, 0x0196
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main:
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        /* --------------     TEST RD/WR REGISTER ACCESS     --------------- */
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        mov   #0x5555,  &CNTRL1         ; CNTRL1
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        mov   &CNTRL1,  &0x0200
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        mov   #0xaaaa,  &CNTRL1
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        mov   &CNTRL1,  &0x0202
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        mov   #0xaaaa,  &CNTRL2         ; CNTRL2
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        mov   &CNTRL2,  &0x0204
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        mov   #0x5555,  &CNTRL2
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        mov   &CNTRL2,  &0x0206
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        mov   #0x55aa,  &CNTRL3         ; CNTRL3
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        mov   &CNTRL3,  &0x0208
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        mov   #0xaa55,  &CNTRL3
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        mov   &CNTRL3,  &0x020A
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        mov   #0xaa55,  &CNTRL4         ; CNTRL4
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        mov   &CNTRL4,  &0x020C
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        mov   #0x55aa,  &CNTRL4
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        mov   &CNTRL4,  &0x020E
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        mov   #0x0001, r15
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        /* ----------------------         END OF TEST        --------------- */
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end_of_test:
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        nop
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        br #0xffff
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        /* ----------------------         INTERRUPT VECTORS  --------------- */
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.section .vectors, "a"
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.word end_of_test  ; Interrupt  0 (lowest priority)    
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.word end_of_test  ; Interrupt  1                      
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.word end_of_test  ; Interrupt  2                      
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.word end_of_test  ; Interrupt  3                      
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.word end_of_test  ; Interrupt  4                      
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.word end_of_test  ; Interrupt  5                      
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.word end_of_test  ; Interrupt  6                      
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.word end_of_test  ; Interrupt  7                      
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.word end_of_test  ; Interrupt  8                      
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.word end_of_test  ; Interrupt  9                      
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.word end_of_test  ; Interrupt 10                      Watchdog timer
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.word end_of_test  ; Interrupt 11                      
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.word end_of_test  ; Interrupt 12                      
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.word end_of_test  ; Interrupt 13                      
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.word end_of_test  ; Interrupt 14                      NMI
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.word main         ; Interrupt 15 (highest priority)   RESET

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