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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart.v] - Blame information for rev 2

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1 2 olivier.girard
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                            DEBUG INTERFACE:  UART                         */
25
/*---------------------------------------------------------------------------*/
26
/* Test the UART debug interface:                                            */
27
/*                        - Check RD/WR access to debugg registers.          */
28
/*                        - Check RD Bursts.                                 */
29
/*                        - Check WR Bursts.                                 */
30
/*===========================================================================*/
31
 
32
`define LONG_TIMEOUT
33
 
34
reg  [3:0] dbg_id_rom;
35
reg  [3:0] dbg_id_ram;
36
reg [31:0] dbg_id;
37
 
38
initial
39
   begin
40
      $display(" ===============================================");
41
      $display("|                 START SIMULATION              |");
42
      $display(" ===============================================");
43
      repeat(30) @(posedge mclk);
44
      stimulus_done = 0;
45
 
46
      // SEND UART SYNCHRONIZATION FRAME
47
      dbg_uart_tx(DBG_SYNC);
48
 
49
      // TEST CPU REGISTERS
50
      //--------------------------------------------------------
51
      dbg_id_rom = `ROM_AWIDTH;
52
      dbg_id_ram = `RAM_AWIDTH;
53
      dbg_id     = {`DBG_ID, dbg_id_rom, dbg_id_ram};
54
 
55
      dbg_uart_wr(CPU_ID_LO  ,  16'hffff);
56
      dbg_uart_rd(CPU_ID_LO);
57
      if (dbg_uart_buf !== dbg_id[15:0])  tb_error("====== CPU_ID_LO uncorrect =====");
58
      dbg_uart_wr(CPU_ID_LO  ,  16'h0000);
59
      dbg_uart_rd(CPU_ID_LO);
60
      if (dbg_uart_buf !== dbg_id[15:0])  tb_error("====== CPU_ID_LO uncorrect =====");
61
 
62
      dbg_uart_wr(CPU_ID_HI  ,  16'hffff);
63
      dbg_uart_rd(CPU_ID_HI);
64
      if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
65
      dbg_uart_wr(CPU_ID_HI  ,  16'h0000);
66
      dbg_uart_rd(CPU_ID_HI);
67
      if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
68
 
69
      dbg_uart_wr(CPU_STAT   ,  16'hffff);
70
      dbg_uart_rd(CPU_STAT);
71
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_STAT uncorrect =====");
72
      dbg_uart_wr(CPU_STAT   ,  16'h0000);
73
      dbg_uart_rd(CPU_STAT);
74
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_STAT uncorrect =====");
75
 
76
      dbg_uart_wr(CPU_CTL    ,  16'hffff);
77
      dbg_uart_rd(CPU_CTL);
78
      if (dbg_uart_buf !== 16'h0078)      tb_error("====== CPU_CTL uncorrect =====");
79
      dbg_uart_wr(CPU_CTL    ,  16'h0000);
80
      dbg_uart_rd(CPU_CTL);
81
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_CTL uncorrect =====");
82
 
83
 
84
      // TEST MEMORY CONTROL REGISTERS
85
      //--------------------------------------------------------
86
 
87
      dbg_uart_wr(MEM_CTL    ,  16'hfffe);
88
      dbg_uart_rd(MEM_CTL);
89
      if (dbg_uart_buf !== 16'h000E)      tb_error("====== MEM_CTL uncorrect =====");
90
      dbg_uart_wr(MEM_CTL    ,  16'h0000);
91
      dbg_uart_rd(MEM_CTL);
92
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_CTL uncorrect =====");
93
 
94
      dbg_uart_wr(MEM_ADDR   ,  16'hffff);
95
      dbg_uart_rd(MEM_ADDR);
96
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_ADDR uncorrect =====");
97
      dbg_uart_wr(MEM_ADDR   ,  16'h0000);
98
      dbg_uart_rd(MEM_ADDR);
99
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_ADDR uncorrect =====");
100
 
101
      dbg_uart_wr(MEM_DATA   ,  16'hffff);
102
      dbg_uart_rd(MEM_DATA);
103
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_DATA uncorrect =====");
104
      dbg_uart_wr(MEM_DATA   ,  16'h0000);
105
      dbg_uart_rd(MEM_DATA);
106
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_DATA uncorrect =====");
107
 
108
      dbg_uart_wr(MEM_CNT    ,  16'hffff);
109
      dbg_uart_rd(MEM_CNT);
110
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_CNT uncorrect =====");
111
      dbg_uart_wr(MEM_CNT    ,  16'h0000);
112
      dbg_uart_rd(MEM_CNT);
113
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_CNT uncorrect =====");
114
 
115
 
116
      // TEST HARDWARE BREAKPOINT 0 REGISTERS
117
      //--------------------------------------------------------
118
 
119
      dbg_uart_wr(BRK0_CTL   ,  16'hffff);
120
      dbg_uart_rd(BRK0_CTL);
121
      if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK0_CTL uncorrect =====");
122
      dbg_uart_wr(BRK0_CTL   ,  16'h0000);
123
      dbg_uart_rd(BRK0_CTL);
124
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_CTL uncorrect =====");
125
 
126
      dbg_uart_wr(BRK0_STAT  ,  16'hffff);
127
      dbg_uart_rd(BRK0_STAT);
128
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_STAT uncorrect =====");
129
      dbg_uart_wr(BRK0_STAT  ,  16'h0000);
130
      dbg_uart_rd(BRK0_STAT);
131
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_STAT uncorrect =====");
132
 
133
      dbg_uart_wr(BRK0_ADDR0 ,  16'hffff);
134
      dbg_uart_rd(BRK0_ADDR0);
135
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK0_ADDR0 uncorrect =====");
136
      dbg_uart_wr(BRK0_ADDR0 ,  16'h0000);
137
      dbg_uart_rd(BRK0_ADDR0);
138
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_ADDR0 uncorrect =====");
139
 
140
      dbg_uart_wr(BRK0_ADDR1 ,  16'hffff);
141
      dbg_uart_rd(BRK0_ADDR1);
142
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK0_ADDR1 uncorrect =====");
143
      dbg_uart_wr(BRK0_ADDR1 ,  16'h0000);
144
      dbg_uart_rd(BRK0_ADDR1);
145
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_ADDR1 uncorrect =====");
146
 
147
 
148
      // TEST HARDWARE BREAKPOINT 1 REGISTERS
149
      //--------------------------------------------------------
150
 
151
      dbg_uart_wr(BRK1_CTL   ,  16'hffff);
152
      dbg_uart_rd(BRK1_CTL);
153
      if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK1_CTL uncorrect =====");
154
      dbg_uart_wr(BRK1_CTL   ,  16'h0000);
155
      dbg_uart_rd(BRK1_CTL);
156
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_CTL uncorrect =====");
157
 
158
      dbg_uart_wr(BRK1_STAT  ,  16'hffff);
159
      dbg_uart_rd(BRK1_STAT);
160
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_STAT uncorrect =====");
161
      dbg_uart_wr(BRK1_STAT  ,  16'h0000);
162
      dbg_uart_rd(BRK1_STAT);
163
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_STAT uncorrect =====");
164
 
165
      dbg_uart_wr(BRK1_ADDR0 ,  16'hffff);
166
      dbg_uart_rd(BRK1_ADDR0);
167
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK1_ADDR0 uncorrect =====");
168
      dbg_uart_wr(BRK1_ADDR0 ,  16'h0000);
169
      dbg_uart_rd(BRK1_ADDR0);
170
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_ADDR0 uncorrect =====");
171
 
172
      dbg_uart_wr(BRK1_ADDR1 ,  16'hffff);
173
      dbg_uart_rd(BRK1_ADDR1);
174
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK1_ADDR1 uncorrect =====");
175
      dbg_uart_wr(BRK1_ADDR1 ,  16'h0000);
176
      dbg_uart_rd(BRK1_ADDR1);
177
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_ADDR1 uncorrect =====");
178
 
179
 
180
      // TEST HARDWARE BREAKPOINT 2 REGISTERS
181
      //--------------------------------------------------------
182
 
183
      dbg_uart_wr(BRK2_CTL   ,  16'hffff);
184
      dbg_uart_rd(BRK2_CTL);
185
      if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK2_CTL uncorrect =====");
186
      dbg_uart_wr(BRK2_CTL   ,  16'h0000);
187
      dbg_uart_rd(BRK2_CTL);
188
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_CTL uncorrect =====");
189
 
190
      dbg_uart_wr(BRK2_STAT  ,  16'hffff);
191
      dbg_uart_rd(BRK2_STAT);
192
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_STAT uncorrect =====");
193
      dbg_uart_wr(BRK2_STAT  ,  16'h0000);
194
      dbg_uart_rd(BRK2_STAT);
195
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_STAT uncorrect =====");
196
 
197
      dbg_uart_wr(BRK2_ADDR0 ,  16'hffff);
198
      dbg_uart_rd(BRK2_ADDR0);
199
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK2_ADDR0 uncorrect =====");
200
      dbg_uart_wr(BRK2_ADDR0 ,  16'h0000);
201
      dbg_uart_rd(BRK2_ADDR0);
202
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_ADDR0 uncorrect =====");
203
 
204
      dbg_uart_wr(BRK2_ADDR1 ,  16'hffff);
205
      dbg_uart_rd(BRK2_ADDR1);
206
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK2_ADDR1 uncorrect =====");
207
      dbg_uart_wr(BRK2_ADDR1 ,  16'h0000);
208
      dbg_uart_rd(BRK2_ADDR1);
209
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_ADDR1 uncorrect =====");
210
 
211
 
212
      // TEST HARDWARE BREAKPOINT 3 REGISTERS
213
      //--------------------------------------------------------
214
 
215
      dbg_uart_wr(BRK3_CTL   ,  16'hffff);
216
      dbg_uart_rd(BRK3_CTL);
217
      if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK3_CTL uncorrect =====");
218
      dbg_uart_wr(BRK3_CTL   ,  16'h0000);
219
      dbg_uart_rd(BRK3_CTL);
220
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_CTL uncorrect =====");
221
 
222
      dbg_uart_wr(BRK3_STAT  ,  16'hffff);
223
      dbg_uart_rd(BRK3_STAT);
224
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_STAT uncorrect =====");
225
      dbg_uart_wr(BRK3_STAT  ,  16'h0000);
226
      dbg_uart_rd(BRK3_STAT);
227
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_STAT uncorrect =====");
228
 
229
      dbg_uart_wr(BRK3_ADDR0 ,  16'hffff);
230
      dbg_uart_rd(BRK3_ADDR0);
231
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK3_ADDR0 uncorrect =====");
232
      dbg_uart_wr(BRK3_ADDR0 ,  16'h0000);
233
      dbg_uart_rd(BRK3_ADDR0);
234
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_ADDR0 uncorrect =====");
235
 
236
      dbg_uart_wr(BRK3_ADDR1 ,  16'hffff);
237
      dbg_uart_rd(BRK3_ADDR1);
238
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK3_ADDR1 uncorrect =====");
239
      dbg_uart_wr(BRK3_ADDR1 ,  16'h0000);
240
      dbg_uart_rd(BRK3_ADDR1);
241
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_ADDR1 uncorrect =====");
242
 
243
 
244
      // TEST 16B WRITE BURSTS (MEMORY)
245
      //--------------------------------------------------------
246
 
247
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
248
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
249
 
250
      dbg_uart_wr(MEM_CTL,  16'h0003); // Start burst to 16 bit memory write
251
      dbg_uart_tx16(16'h1234);         // write 1st data
252
      repeat(10) @(posedge mclk);
253
      if (mem200 !== 16'h1234)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
254
      dbg_uart_tx16(16'h5678);         // write 2nd data
255
      repeat(10) @(posedge mclk);
256
      if (mem202 !== 16'h5678)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
257
      dbg_uart_tx16(16'h9abc);         // write 3rd data
258
      repeat(10) @(posedge mclk);
259
      if (mem204 !== 16'h9abc)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
260
      dbg_uart_tx16(16'hdef0);         // write 4th data
261
      repeat(10) @(posedge mclk);
262
      if (mem206 !== 16'hdef0)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
263
      dbg_uart_tx16(16'h0fed);         // write 5th data
264
      repeat(10) @(posedge mclk);
265
      if (mem208 !== 16'h0fed)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
266
 
267
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
268
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
269
 
270
      dbg_uart_wr(MEM_CTL,  16'h0001); // Start burst to 16 bit registers read
271
      dbg_uart_rx16();                 // read 1st data
272
      if (dbg_uart_buf !== 16'h1234)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
273
      dbg_uart_rx16();                 // read 2nd data
274
      if (dbg_uart_buf !== 16'h5678)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
275
      dbg_uart_rx16();                 // read 3rd data
276
      if (dbg_uart_buf !== 16'h9abc)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
277
      dbg_uart_rx16();                 // read 4th data
278
      if (dbg_uart_buf !== 16'hdef0)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
279
      dbg_uart_rx16();                 // read 5th data
280
      if (dbg_uart_buf !== 16'h0fed)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
281
 
282
 
283
      // TEST 16B WRITE BURSTS (CPU REGISTERS)
284
      //--------------------------------------------------------
285
 
286
      dbg_uart_wr(MEM_ADDR, 16'h0005); // select R5
287
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
288
 
289
      dbg_uart_wr(MEM_CTL,  16'h0007); // Start burst to 16 bit cpu register write
290
      dbg_uart_tx16(16'hcba9);         // write 1st data
291
      repeat(10) @(posedge mclk);
292
      if (r5 !== 16'hcba9)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 1st DATA =====");
293
      dbg_uart_tx16(16'h8765);         // write 2nd data
294
      repeat(10) @(posedge mclk);
295
      if (r6 !== 16'h8765)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 2nd DATA =====");
296
      dbg_uart_tx16(16'h4321);         // write 3rd data
297
      repeat(10) @(posedge mclk);
298
      if (r7 !== 16'h4321)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 3rd DATA =====");
299
      dbg_uart_tx16(16'h0123);         // write 4th data
300
      repeat(10) @(posedge mclk);
301
      if (r8 !== 16'h0123)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 4th DATA =====");
302
      dbg_uart_tx16(16'h4567);         // write 5th data
303
      repeat(10) @(posedge mclk);
304
      if (r9 !== 16'h4567)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 5th DATA =====");
305
 
306
      dbg_uart_wr(MEM_ADDR, 16'h0005); // select @0x0200
307
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
308
 
309
      dbg_uart_wr(MEM_CTL,  16'h0005); // Start burst to 16 bit cpu registers read
310
      dbg_uart_rx16();                 // read 1st data
311
      if (dbg_uart_buf !== 16'hcba9)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 1st DATA =====");
312
      dbg_uart_rx16();                 // read 2nd data
313
      if (dbg_uart_buf !== 16'h8765)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 2nd DATA =====");
314
      dbg_uart_rx16();                 // read 3rd data
315
      if (dbg_uart_buf !== 16'h4321)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 3rd DATA =====");
316
      dbg_uart_rx16();                 // read 4th data
317
      if (dbg_uart_buf !== 16'h0123)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 4th DATA =====");
318
      dbg_uart_rx16();                 // read 5th data
319
      if (dbg_uart_buf !== 16'h4567)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 5th DATA =====");
320
 
321
 
322
      // TEST 8B WRITE BURSTS (MEMORY)
323
      //--------------------------------------------------------
324
 
325
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0210
326
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
327
 
328
      dbg_uart_wr(MEM_CTL,  16'h000b); // Start burst to 8 bit memory write
329
      dbg_uart_tx(8'h91);         // write 1st data
330
      repeat(10) @(posedge mclk);
331
      if (mem200 !== 16'h1291)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
332
      dbg_uart_tx(8'h82);         // write 2nd data
333
      repeat(10) @(posedge mclk);
334
      if (mem200 !== 16'h8291)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
335
      dbg_uart_tx(8'h73);         // write 3rd data
336
      repeat(10) @(posedge mclk);
337
      if (mem202 !== 16'h5673)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
338
      dbg_uart_tx(8'h64);         // write 4th data
339
      repeat(10) @(posedge mclk);
340
      if (mem202 !== 16'h6473)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
341
      dbg_uart_tx(8'h55);         // write 5th data
342
      repeat(10) @(posedge mclk);
343
      if (mem204 !== 16'h9a55)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
344
 
345
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
346
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
347
 
348
      dbg_uart_wr(MEM_CTL,  16'h0009); // Start burst to 8 bit registers read
349
      dbg_uart_rx8();                 // read 1st data
350
      if (dbg_uart_buf !== 16'h0091)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
351
      dbg_uart_rx8();                 // read 2nd data
352
      if (dbg_uart_buf !== 16'h0082)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
353
      dbg_uart_rx8();                 // read 3rd data
354
      if (dbg_uart_buf !== 16'h0073)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
355
      dbg_uart_rx8();                 // read 4th data
356
      if (dbg_uart_buf !== 16'h0064)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
357
      dbg_uart_rx8();                 // read 5th data
358
      if (dbg_uart_buf !== 16'h0055)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
359
 
360
 
361
 
362
 
363
 
364
      dbg_uart_wr(CPU_CTL    ,  16'h0002);
365
      repeat(10) @(posedge mclk);
366
 
367
      stimulus_done = 1;
368
   end
369
 

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