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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart.s43] - Blame information for rev 141

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1 2 olivier.girard
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                            DEBUG INTERFACE:  UART                         */
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/*---------------------------------------------------------------------------*/
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/* Test the UART debug interface:                                            */
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/*                        - Check RD/WR access to debugg registers.          */
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/*                        - Check RD Bursts.                                 */
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/*                        - Check WR Bursts.                                 */
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
35 19 olivier.girard
/* $Rev: 141 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $          */
38 2 olivier.girard
/*===========================================================================*/
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40 141 olivier.girard
.include "pmem_defs.asm"
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42 2 olivier.girard
.global main
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WAIT_FUNC:
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        dec r14
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        jnz WAIT_FUNC
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        ret
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main:
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        mov #DMEM_250, r1       ; # Initialize stack pointer
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        mov   #0x0000, &DMEM_200
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        mov   #0x0000, r15
54 2 olivier.girard
 
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56 111 olivier.girard
        mov   #0x0300, r14
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        call  #WAIT_FUNC
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59 111 olivier.girard
        mov   #0x1000, r15
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        /* ----------------------         END OF TEST        --------------- */
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end_of_test:
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        nop
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        br #0xffff
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        /* ----------------------         INTERRUPT VECTORS  --------------- */
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.section .vectors, "a"
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.word end_of_test        ; Interrupt  0 (lowest priority)    
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.word end_of_test        ; Interrupt  1                      
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.word end_of_test        ; Interrupt  2                      
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.word end_of_test        ; Interrupt  3                      
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.word end_of_test        ; Interrupt  4                      
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.word end_of_test        ; Interrupt  5                      
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.word end_of_test        ; Interrupt  6                      
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.word end_of_test        ; Interrupt  7                      
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.word end_of_test        ; Interrupt  8                      
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.word end_of_test        ; Interrupt  9                      
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.word end_of_test        ; Interrupt 10                      Watchdog timer
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.word end_of_test        ; Interrupt 11                      
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.word end_of_test        ; Interrupt 12                      
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.word end_of_test        ; Interrupt 13                      
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.word end_of_test        ; Interrupt 14                      NMI
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.word main               ; Interrupt 15 (highest priority)   RESET

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