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1 2 olivier.girard
//----------------------------------------------------------------------------
2
// Copyright (C) 2001 Authors
3
//
4
// This source file may be used and distributed without restriction provided
5
// that this copyright statement is not removed from the file and that any
6
// derivative work contains the original copyright notice and the associated
7
// disclaimer.
8
//
9
// This source file is free software; you can redistribute it and/or modify
10
// it under the terms of the GNU Lesser General Public License as published
11
// by the Free Software Foundation; either version 2.1 of the License, or
12
// (at your option) any later version.
13
//
14
// This source is distributed in the hope that it will be useful, but WITHOUT
15
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
17
// License for more details.
18
//
19
// You should have received a copy of the GNU Lesser General Public License
20
// along with this source; if not, write to the Free Software Foundation,
21
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
22
//
23
//----------------------------------------------------------------------------
24
//
25 34 olivier.girard
// *File Name: omsp_frontend.v
26 2 olivier.girard
// 
27
// *Module Description:
28
//                       openMSP430 Instruction fetch and decode unit
29
//
30
// *Author(s):
31
//              - Olivier Girard,    olgirard@gmail.com
32
//
33
//----------------------------------------------------------------------------
34 17 olivier.girard
// $Rev: 103 $
35
// $LastChangedBy: olivier.girard $
36
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
37
//----------------------------------------------------------------------------
38 103 olivier.girard
`ifdef OMSP_NO_INCLUDE
39
`else
40 23 olivier.girard
`include "openMSP430_defines.v"
41 103 olivier.girard
`endif
42 2 olivier.girard
 
43 34 olivier.girard
module  omsp_frontend (
44 2 olivier.girard
 
45
// OUTPUTs
46
    dbg_halt_st,                   // Halt/Run status from CPU
47 53 olivier.girard
    decode_noirq,                  // Frontend decode instruction
48 2 olivier.girard
    e_state,                       // Execution state
49
    exec_done,                     // Execution completed
50
    inst_ad,                       // Decoded Inst: destination addressing mode
51
    inst_as,                       // Decoded Inst: source addressing mode
52
    inst_alu,                      // ALU control signals
53
    inst_bw,                       // Decoded Inst: byte width
54
    inst_dest,                     // Decoded Inst: destination (one hot)
55
    inst_dext,                     // Decoded Inst: destination extended instruction word
56
    inst_irq_rst,                  // Decoded Inst: Reset interrupt
57
    inst_jmp,                      // Decoded Inst: Conditional jump
58
    inst_sext,                     // Decoded Inst: source extended instruction word
59
    inst_so,                       // Decoded Inst: Single-operand arithmetic
60
    inst_src,                      // Decoded Inst: source (one hot)
61
    inst_type,                     // Decoded Instruction type
62
    irq_acc,                       // Interrupt request accepted (one-hot signal)
63
    mab,                           // Frontend Memory address bus
64
    mb_en,                         // Frontend Memory bus enable
65
    nmi_acc,                       // Non-Maskable interrupt request accepted
66
    pc,                            // Program counter
67
    pc_nxt,                        // Next PC value (for CALL & IRQ)
68
 
69
// INPUTs
70
    cpuoff,                        // Turns off the CPU
71
    dbg_halt_cmd,                  // Halt CPU command
72
    dbg_reg_sel,                   // Debug selected register for rd/wr access
73 33 olivier.girard
    fe_pmem_wait,                  // Frontend wait for Instruction fetch
74 2 olivier.girard
    gie,                           // General interrupt enable
75
    irq,                           // Maskable interrupts
76
    mclk,                          // Main system clock
77
    mdb_in,                        // Frontend Memory data bus input
78
    nmi_evt,                       // Non-maskable interrupt event
79
    pc_sw,                         // Program counter software value
80
    pc_sw_wr,                      // Program counter software write
81
    puc,                           // Main system reset
82
    wdt_irq                        // Watchdog-timer interrupt
83
);
84
 
85
// OUTPUTs
86
//=========
87
output              dbg_halt_st;   // Halt/Run status from CPU
88 53 olivier.girard
output              decode_noirq;  // Frontend decode instruction
89 2 olivier.girard
output        [3:0] e_state;       // Execution state
90
output              exec_done;     // Execution completed
91
output        [7:0] inst_ad;       // Decoded Inst: destination addressing mode
92
output        [7:0] inst_as;       // Decoded Inst: source addressing mode
93
output       [11:0] inst_alu;      // ALU control signals
94
output              inst_bw;       // Decoded Inst: byte width
95
output       [15:0] inst_dest;     // Decoded Inst: destination (one hot)
96
output       [15:0] inst_dext;     // Decoded Inst: destination extended instruction word
97
output              inst_irq_rst;  // Decoded Inst: Reset interrupt
98
output        [7:0] inst_jmp;      // Decoded Inst: Conditional jump
99
output       [15:0] inst_sext;     // Decoded Inst: source extended instruction word
100
output        [7:0] inst_so;       // Decoded Inst: Single-operand arithmetic
101
output       [15:0] inst_src;      // Decoded Inst: source (one hot)
102
output        [2:0] inst_type;     // Decoded Instruction type
103
output       [13:0] irq_acc;       // Interrupt request accepted (one-hot signal)
104
output       [15:0] mab;           // Frontend Memory address bus
105
output              mb_en;         // Frontend Memory bus enable
106
output              nmi_acc;       // Non-Maskable interrupt request accepted
107
output       [15:0] pc;            // Program counter
108
output       [15:0] pc_nxt;        // Next PC value (for CALL & IRQ)
109
 
110
// INPUTs
111
//=========
112
input               cpuoff;        // Turns off the CPU
113
input               dbg_halt_cmd;  // Halt CPU command
114
input         [3:0] dbg_reg_sel;   // Debug selected register for rd/wr access
115 33 olivier.girard
input               fe_pmem_wait;  // Frontend wait for Instruction fetch
116 2 olivier.girard
input               gie;           // General interrupt enable
117
input        [13:0] irq;           // Maskable interrupts
118
input               mclk;          // Main system clock
119
input        [15:0] mdb_in;        // Frontend Memory data bus input
120
input               nmi_evt;       // Non-maskable interrupt event
121
input        [15:0] pc_sw;         // Program counter software value
122
input               pc_sw_wr;      // Program counter software write
123
input               puc;           // Main system reset
124
input               wdt_irq;       // Watchdog-timer interrupt
125
 
126
 
127
//=============================================================================
128 85 olivier.girard
// 0)  UTILITY FUNCTIONS
129
//=============================================================================
130
 
131
// 16 bits one-hot decoder
132
function [15:0] one_hot16;
133
   input  [3:0] binary;
134
   begin
135
      one_hot16         = 16'h0000;
136
      one_hot16[binary] =  1'b1;
137
   end
138
endfunction
139
 
140
// 8 bits one-hot decoder
141
function [7:0] one_hot8;
142
   input  [2:0] binary;
143
   begin
144
      one_hot8         = 8'h00;
145
      one_hot8[binary] = 1'b1;
146
   end
147
endfunction
148
 
149
 
150
//=============================================================================
151 2 olivier.girard
// 1)  FRONTEND STATE MACHINE
152
//=============================================================================
153
 
154
// The wire "conv" is used as state bits to calculate the next response
155
reg  [2:0] i_state;
156
reg  [2:0] i_state_nxt;
157
 
158
reg  [1:0] inst_sz;
159
wire [1:0] inst_sz_nxt;
160
wire       irq_detect;
161
wire [2:0] inst_type_nxt;
162
wire       is_const;
163
reg [15:0] sconst_nxt;
164
reg  [3:0] e_state_nxt;
165
 
166
// State machine definitons
167
parameter I_IRQ_FETCH = 3'h0;
168
parameter I_IRQ_DONE  = 3'h1;
169
parameter I_DEC       = 3'h2; // New instruction ready for decode
170
parameter I_EXT1      = 3'h3; // 1st Extension word
171
parameter I_EXT2      = 3'h4; // 2nd Extension word
172
parameter I_IDLE      = 3'h5; // CPU is in IDLE mode
173
 
174
// States Transitions
175
always @(i_state   or inst_sz    or inst_sz_nxt or pc_sw_wr     or exec_done or
176
         exec_done or irq_detect or cpuoff      or dbg_halt_cmd or e_state)
177
    case(i_state)
178
      I_IDLE     : i_state_nxt = (irq_detect & ~dbg_halt_cmd) ? I_IRQ_FETCH :
179
                                 (~cpuoff    & ~dbg_halt_cmd) ? I_DEC       : I_IDLE;
180
      I_IRQ_FETCH: i_state_nxt =  I_IRQ_DONE;
181
      I_IRQ_DONE : i_state_nxt =  I_DEC;
182
      I_DEC      : i_state_nxt =  irq_detect                  ? I_IRQ_FETCH :
183
                          (cpuoff | dbg_halt_cmd) & exec_done ? I_IDLE      :
184
                            dbg_halt_cmd & (e_state==`E_IDLE) ? I_IDLE      :
185
                                  pc_sw_wr                    ? I_DEC       :
186
                             ~exec_done & ~(e_state==`E_IDLE) ? I_DEC       :        // Wait in decode state
187
                                  (inst_sz_nxt!=2'b00)        ? I_EXT1      : I_DEC; // until execution is completed
188
      I_EXT1     : i_state_nxt =  irq_detect                  ? I_IRQ_FETCH :
189
                                  pc_sw_wr                    ? I_DEC       :
190
                                  (inst_sz!=2'b01)            ? I_EXT2      : I_DEC;
191
      I_EXT2     : i_state_nxt =  irq_detect                  ? I_IRQ_FETCH : I_DEC;
192
      default    : i_state_nxt =  I_IRQ_FETCH;
193
    endcase
194
 
195
// State machine
196
always @(posedge mclk or posedge puc)
197
  if (puc) i_state  <= I_IRQ_FETCH;
198
  else     i_state  <= i_state_nxt;
199
 
200
// Utility signals
201 53 olivier.girard
wire   decode_noirq =  ((i_state==I_DEC) &  (exec_done | (e_state==`E_IDLE)));
202
wire   decode       =  decode_noirq | irq_detect;
203
wire   fetch        = ~((i_state==I_DEC) & ~(exec_done | (e_state==`E_IDLE))) & ~(e_state_nxt==`E_IDLE);
204 2 olivier.girard
 
205
// Debug interface cpu status
206
reg    dbg_halt_st;
207
always @(posedge mclk or posedge puc)
208
  if (puc)  dbg_halt_st <= 1'b0;
209
  else      dbg_halt_st <= dbg_halt_cmd & (i_state_nxt==I_IDLE);
210
 
211
 
212
//=============================================================================
213
// 2)  INTERRUPT HANDLING
214
//=============================================================================
215
 
216
// Detect nmi interrupt
217
reg         inst_nmi;
218
always @(posedge mclk or posedge puc)
219
  if (puc)                      inst_nmi <= 1'b0;
220
  else if (nmi_evt)             inst_nmi <= 1'b1;
221
  else if (i_state==I_IRQ_DONE) inst_nmi <= 1'b0;
222
 
223
 
224
// Detect reset interrupt
225
reg         inst_irq_rst;
226
always @(posedge mclk or posedge puc)
227
  if (puc)                      inst_irq_rst <= 1'b1;
228
  else if (exec_done)           inst_irq_rst <= 1'b0;
229
 
230
//  Detect other interrupts
231 91 olivier.girard
assign  irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~dbg_halt_cmd & ~dbg_halt_st & (exec_done | (i_state==I_IDLE));
232 2 olivier.girard
 
233
// Select interrupt vector
234
reg  [3:0] irq_num;
235
always @(posedge mclk or posedge puc)
236
  if (puc)             irq_num <= 4'hf;
237
  else if (irq_detect) irq_num <= inst_nmi           ?  4'he :
238
                                  irq[13]            ?  4'hd :
239
                                  irq[12]            ?  4'hc :
240
                                  irq[11]            ?  4'hb :
241
                                 (irq[10] | wdt_irq) ?  4'ha :
242
                                  irq[9]             ?  4'h9 :
243
                                  irq[8]             ?  4'h8 :
244
                                  irq[7]             ?  4'h7 :
245
                                  irq[6]             ?  4'h6 :
246
                                  irq[5]             ?  4'h5 :
247
                                  irq[4]             ?  4'h4 :
248
                                  irq[3]             ?  4'h3 :
249
                                  irq[2]             ?  4'h2 :
250
                                  irq[1]             ?  4'h1 :
251
                                  irq[0]             ?  4'h0 : 4'hf;
252
 
253
wire [15:0] irq_addr    = {11'h7ff, irq_num, 1'b0};
254
 
255
// Interrupt request accepted
256 85 olivier.girard
wire [15:0] irq_acc_all = one_hot16(irq_num) & {16{(i_state==I_IRQ_FETCH)}};
257 2 olivier.girard
wire [13:0] irq_acc     = irq_acc_all[13:0];
258
wire        nmi_acc     = irq_acc_all[14];
259
 
260
 
261
//=============================================================================
262
// 3)  FETCH INSTRUCTION
263
//=============================================================================
264
 
265
//
266
// 3.1) PROGRAM COUNTER & MEMORY INTERFACE
267
//-----------------------------------------
268
 
269
// Program counter
270
reg  [15:0] pc;
271
 
272 60 olivier.girard
// Compute next PC value
273
wire [15:0] pc_incr = pc + {14'h0000, fetch, 1'b0};
274
wire [15:0] pc_nxt  = pc_sw_wr               ? pc_sw    :
275 2 olivier.girard
                      (i_state==I_IRQ_FETCH) ? irq_addr :
276 60 olivier.girard
                      (i_state==I_IRQ_DONE)  ? mdb_in   :  pc_incr;
277 2 olivier.girard
 
278
always @(posedge mclk or posedge puc)
279
  if (puc)  pc <= 16'h0000;
280
  else      pc <= pc_nxt;
281
 
282
// Check if ROM has been busy in order to retry ROM access
283 33 olivier.girard
reg pmem_busy;
284 2 olivier.girard
always @(posedge mclk or posedge puc)
285 85 olivier.girard
  if (puc)  pmem_busy <= 1'b0;
286 33 olivier.girard
  else      pmem_busy <= fe_pmem_wait;
287 2 olivier.girard
 
288
// Memory interface
289
wire [15:0] mab      = pc_nxt;
290 33 olivier.girard
wire        mb_en    = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~dbg_halt_cmd);
291 2 olivier.girard
 
292
 
293
//
294
// 3.2) INSTRUCTION REGISTER
295
//--------------------------------
296
 
297
// Instruction register
298
wire [15:0] ir  = mdb_in;
299
 
300
// Detect if source extension word is required
301
wire is_sext = (inst_as[`IDX] | inst_as[`SYMB] | inst_as[`ABS] | inst_as[`IMM]);
302
 
303
// Detect if destination extension word is required
304
wire is_dext = (inst_ad[`IDX] | inst_ad[`SYMB] | inst_ad[`ABS]);
305
 
306
// For the Symbolic addressing mode, add -2 to the extension word in order
307
// to make up for the PC address
308
wire [15:0] ext_incr = ((i_state==I_EXT1)     &  inst_as[`SYMB]) |
309
                       ((i_state==I_EXT2)     &  inst_ad[`SYMB]) |
310
                       ((i_state==I_EXT1)     & ~inst_as[`SYMB] &
311
                       ~(i_state_nxt==I_EXT2) &  inst_ad[`SYMB])   ? 16'hfffe : 16'h0000;
312
 
313
wire [15:0] ext_nxt  = ir + ext_incr;
314
 
315
// Store source extension word
316
reg [15:0] inst_sext;
317
always @(posedge mclk or posedge puc)
318
  if (puc)                                     inst_sext <= 16'h0000;
319
  else if (decode & is_const)                  inst_sext <= sconst_nxt;
320
  else if (decode & inst_type_nxt[`INST_JMP])  inst_sext <= {{5{ir[9]}},ir[9:0],1'b0};
321
  else if ((i_state==I_EXT1) & is_sext)        inst_sext <= ext_nxt;
322
 
323
// Source extension word is ready
324
wire inst_sext_rdy = (i_state==I_EXT1) & is_sext;
325
 
326
 
327
// Store destination extension word
328
reg [15:0] inst_dext;
329
always @(posedge mclk or posedge puc)
330
  if (puc)                               inst_dext <= 16'h0000;
331
  else if ((i_state==I_EXT1) & ~is_sext) inst_dext <= ext_nxt;
332
  else if  (i_state==I_EXT2)             inst_dext <= ext_nxt;
333
 
334
// Destination extension word is ready
335
wire inst_dext_rdy = (((i_state==I_EXT1) & ~is_sext) | (i_state==I_EXT2));
336
 
337
 
338
//=============================================================================
339
// 4)  DECODE INSTRUCTION
340
//=============================================================================
341
 
342
//
343
// 4.1) OPCODE: INSTRUCTION TYPE
344
//----------------------------------------
345
// Instructions type is encoded in a one hot fashion as following:
346
//
347
// 3'b001: Single-operand arithmetic
348
// 3'b010: Conditional jump
349
// 3'b100: Two-operand arithmetic
350
 
351
reg  [2:0] inst_type;
352
assign     inst_type_nxt = {(ir[15:14]!=2'b00),
353
                            (ir[15:13]==3'b001),
354
                            (ir[15:13]==3'b000)} & {3{~irq_detect}};
355
 
356
always @(posedge mclk or posedge puc)
357
  if (puc)                      inst_type <= 3'b000;
358
  else if (decode)              inst_type <= inst_type_nxt;
359
 
360
//
361
// 4.2) OPCODE: SINGLE-OPERAND ARITHMETIC
362
//----------------------------------------
363
// Instructions are encoded in a one hot fashion as following:
364
//
365
// 8'b00000001: RRC
366
// 8'b00000010: SWPB
367
// 8'b00000100: RRA
368
// 8'b00001000: SXT
369
// 8'b00010000: PUSH
370
// 8'b00100000: CALL
371
// 8'b01000000: RETI
372
// 8'b10000000: IRQ
373
 
374
reg   [7:0] inst_so;
375 85 olivier.girard
wire  [7:0] inst_so_nxt = irq_detect ? 8'h80 : (one_hot8(ir[9:7]) & {8{inst_type_nxt[`INST_SO]}});
376 2 olivier.girard
 
377
always @(posedge mclk or posedge puc)
378
  if (puc)         inst_so <= 8'h00;
379
  else if (decode) inst_so <= inst_so_nxt;
380
 
381
//
382
// 4.3) OPCODE: CONDITIONAL JUMP
383
//--------------------------------
384
// Instructions are encoded in a one hot fashion as following:
385
//
386
// 8'b00000001: JNE/JNZ
387
// 8'b00000010: JEQ/JZ
388
// 8'b00000100: JNC/JLO
389
// 8'b00001000: JC/JHS
390
// 8'b00010000: JN
391
// 8'b00100000: JGE
392
// 8'b01000000: JL
393
// 8'b10000000: JMP
394
 
395
reg   [2:0] inst_jmp_bin;
396
always @(posedge mclk or posedge puc)
397
  if (puc)         inst_jmp_bin <= 3'h0;
398
  else if (decode) inst_jmp_bin <= ir[12:10];
399
 
400 85 olivier.girard
wire [7:0] inst_jmp = one_hot8(inst_jmp_bin) & {8{inst_type[`INST_JMP]}};
401 2 olivier.girard
 
402
 
403
//
404
// 4.4) OPCODE: TWO-OPERAND ARITHMETIC
405
//-------------------------------------
406
// Instructions are encoded in a one hot fashion as following:
407
//
408
// 12'b000000000001: MOV
409
// 12'b000000000010: ADD
410
// 12'b000000000100: ADDC
411
// 12'b000000001000: SUBC
412
// 12'b000000010000: SUB
413
// 12'b000000100000: CMP
414
// 12'b000001000000: DADD
415
// 12'b000010000000: BIT
416
// 12'b000100000000: BIC
417
// 12'b001000000000: BIS
418
// 12'b010000000000: XOR
419
// 12'b100000000000: AND
420
 
421 85 olivier.girard
wire [15:0] inst_to_1hot = one_hot16(ir[15:12]) & {16{inst_type_nxt[`INST_TO]}};
422 2 olivier.girard
wire [11:0] inst_to_nxt  = inst_to_1hot[15:4];
423
 
424
 
425
//
426
// 4.5) SOURCE AND DESTINATION REGISTERS
427
//---------------------------------------
428
 
429
// Destination register
430
reg [3:0] inst_dest_bin;
431
always @(posedge mclk or posedge puc)
432
  if (puc)         inst_dest_bin <= 4'h0;
433
  else if (decode) inst_dest_bin <= ir[3:0];
434
 
435 85 olivier.girard
wire  [15:0] inst_dest = dbg_halt_st          ? one_hot16(dbg_reg_sel) :
436
                         inst_type[`INST_JMP] ? 16'h0001               :
437 2 olivier.girard
                         inst_so[`IRQ]  |
438
                         inst_so[`PUSH] |
439 85 olivier.girard
                         inst_so[`CALL]       ? 16'h0002               :
440
                                                one_hot16(inst_dest_bin);
441 2 olivier.girard
 
442
 
443
// Source register
444
reg [3:0] inst_src_bin;
445
always @(posedge mclk or posedge puc)
446
  if (puc)         inst_src_bin <= 4'h0;
447
  else if (decode) inst_src_bin <= ir[11:8];
448
 
449 85 olivier.girard
wire  [15:0] inst_src = inst_type[`INST_TO] ? one_hot16(inst_src_bin)  :
450
                        inst_so[`RETI]      ? 16'h0002                 :
451
                        inst_so[`IRQ]       ? 16'h0001                 :
452
                        inst_type[`INST_SO] ? one_hot16(inst_dest_bin) : 16'h0000;
453 2 olivier.girard
 
454
 
455
//
456
// 4.6) SOURCE ADDRESSING MODES
457
//--------------------------------
458
// Source addressing modes are encoded in a one hot fashion as following:
459
//
460
// 13'b0000000000001: Register direct.
461
// 13'b0000000000010: Register indexed.
462
// 13'b0000000000100: Register indirect.
463
// 13'b0000000001000: Register indirect autoincrement.
464
// 13'b0000000010000: Symbolic (operand is in memory at address PC+x).
465
// 13'b0000000100000: Immediate (operand is next word in the instruction stream).
466
// 13'b0000001000000: Absolute (operand is in memory at address x).
467
// 13'b0000010000000: Constant 4.
468
// 13'b0000100000000: Constant 8.
469
// 13'b0001000000000: Constant 0.
470
// 13'b0010000000000: Constant 1.
471
// 13'b0100000000000: Constant 2.
472
// 13'b1000000000000: Constant -1.
473
 
474
reg [12:0] inst_as_nxt;
475
 
476
wire [3:0] src_reg = inst_type_nxt[`INST_SO] ? ir[3:0] : ir[11:8];
477
 
478
always @(src_reg or ir or inst_type_nxt)
479
  begin
480
     if (inst_type_nxt[`INST_JMP])
481
       inst_as_nxt =  13'b0000000000001;
482
     else if (src_reg==4'h3) // Addressing mode using R3
483
       case (ir[5:4])
484
         2'b11  : inst_as_nxt =  13'b1000000000000;
485
         2'b10  : inst_as_nxt =  13'b0100000000000;
486
         2'b01  : inst_as_nxt =  13'b0010000000000;
487
         default: inst_as_nxt =  13'b0001000000000;
488
       endcase
489
     else if (src_reg==4'h2) // Addressing mode using R2
490
       case (ir[5:4])
491
         2'b11  : inst_as_nxt =  13'b0000100000000;
492
         2'b10  : inst_as_nxt =  13'b0000010000000;
493
         2'b01  : inst_as_nxt =  13'b0000001000000;
494
         default: inst_as_nxt =  13'b0000000000001;
495
       endcase
496
     else if (src_reg==4'h0) // Addressing mode using R0
497
       case (ir[5:4])
498
         2'b11  : inst_as_nxt =  13'b0000000100000;
499
         2'b10  : inst_as_nxt =  13'b0000000000100;
500
         2'b01  : inst_as_nxt =  13'b0000000010000;
501
         default: inst_as_nxt =  13'b0000000000001;
502
       endcase
503
     else                    // General Addressing mode
504
       case (ir[5:4])
505
         2'b11  : inst_as_nxt =  13'b0000000001000;
506
         2'b10  : inst_as_nxt =  13'b0000000000100;
507
         2'b01  : inst_as_nxt =  13'b0000000000010;
508
         default: inst_as_nxt =  13'b0000000000001;
509
       endcase
510
  end
511
assign    is_const = |inst_as_nxt[12:7];
512
 
513
reg [7:0] inst_as;
514
always @(posedge mclk or posedge puc)
515
  if (puc)         inst_as <= 8'h00;
516
  else if (decode) inst_as <= {is_const, inst_as_nxt[6:0]};
517
 
518
 
519
// 13'b0000010000000: Constant 4.
520
// 13'b0000100000000: Constant 8.
521
// 13'b0001000000000: Constant 0.
522
// 13'b0010000000000: Constant 1.
523
// 13'b0100000000000: Constant 2.
524
// 13'b1000000000000: Constant -1.
525
always @(inst_as_nxt)
526
  begin
527
     if (inst_as_nxt[7])        sconst_nxt = 16'h0004;
528
     else if (inst_as_nxt[8])   sconst_nxt = 16'h0008;
529
     else if (inst_as_nxt[9])   sconst_nxt = 16'h0000;
530
     else if (inst_as_nxt[10])  sconst_nxt = 16'h0001;
531
     else if (inst_as_nxt[11])  sconst_nxt = 16'h0002;
532
     else if (inst_as_nxt[12])  sconst_nxt = 16'hffff;
533
     else                       sconst_nxt = 16'h0000;
534
  end
535
 
536
 
537
//
538
// 4.7) DESTINATION ADDRESSING MODES
539
//-----------------------------------
540
// Destination addressing modes are encoded in a one hot fashion as following:
541
//
542
// 8'b00000001: Register direct.
543
// 8'b00000010: Register indexed.
544
// 8'b00010000: Symbolic (operand is in memory at address PC+x).
545
// 8'b01000000: Absolute (operand is in memory at address x).
546
 
547
reg  [7:0] inst_ad_nxt;
548
 
549
wire [3:0] dest_reg = ir[3:0];
550
 
551
always @(dest_reg or ir or inst_type_nxt)
552
  begin
553
     if (~inst_type_nxt[`INST_TO])
554
       inst_ad_nxt =  8'b00000000;
555
     else if (dest_reg==4'h2)   // Addressing mode using R2
556
       case (ir[7])
557
         1'b1   : inst_ad_nxt =  8'b01000000;
558
         default: inst_ad_nxt =  8'b00000001;
559
       endcase
560
     else if (dest_reg==4'h0)   // Addressing mode using R0
561
       case (ir[7])
562
         2'b1   : inst_ad_nxt =  8'b00010000;
563
         default: inst_ad_nxt =  8'b00000001;
564
       endcase
565
     else                       // General Addressing mode
566
       case (ir[7])
567
         2'b1   : inst_ad_nxt =  8'b00000010;
568
         default: inst_ad_nxt =  8'b00000001;
569
       endcase
570
  end
571
 
572
reg [7:0] inst_ad;
573
always @(posedge mclk or posedge puc)
574
  if (puc)         inst_ad <= 8'h00;
575
  else if (decode) inst_ad <= inst_ad_nxt;
576
 
577
 
578
//
579
// 4.8) REMAINING INSTRUCTION DECODING
580
//-------------------------------------
581
 
582
// Operation size
583
reg       inst_bw;
584
always @(posedge mclk or posedge puc)
585
  if (puc)         inst_bw     <= 1'b0;
586
  else if (decode) inst_bw     <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~dbg_halt_cmd;
587
 
588
// Extended instruction size
589
assign    inst_sz_nxt = {1'b0,  (inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS] | inst_as_nxt[`IMM])} +
590
                        {1'b0, ((inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS]) & ~inst_type_nxt[`INST_SO])};
591
always @(posedge mclk or posedge puc)
592
  if (puc)         inst_sz     <= 2'b00;
593
  else if (decode) inst_sz     <= inst_sz_nxt;
594
 
595
 
596
//=============================================================================
597
// 5)  EXECUTION-UNIT STATE MACHINE
598
//=============================================================================
599
 
600
// State machine registers
601
reg  [3:0] e_state;
602
 
603
 
604
// State machine control signals
605
//--------------------------------
606
 
607
wire src_acalc_pre =  inst_as_nxt[`IDX]   | inst_as_nxt[`SYMB]    | inst_as_nxt[`ABS];
608
wire src_rd_pre    =  inst_as_nxt[`INDIR] | inst_as_nxt[`INDIR_I] | inst_as_nxt[`IMM]  | inst_so_nxt[`RETI];
609
wire dst_acalc_pre =  inst_ad_nxt[`IDX]   | inst_ad_nxt[`SYMB]    | inst_ad_nxt[`ABS];
610
wire dst_acalc     =  inst_ad[`IDX]       | inst_ad[`SYMB]        | inst_ad[`ABS];
611
wire dst_rd_pre    =  inst_ad_nxt[`IDX]   | inst_so_nxt[`PUSH]    | inst_so_nxt[`CALL] | inst_so_nxt[`RETI];
612
wire dst_rd        =  inst_ad[`IDX]       | inst_so[`PUSH]        | inst_so[`CALL]     | inst_so[`RETI];
613
 
614
wire inst_branch   =  (inst_ad_nxt[`DIR] & (ir[3:0]==4'h0)) | inst_type_nxt[`INST_JMP] | inst_so_nxt[`RETI];
615
 
616
reg exec_jmp;
617
always @(posedge mclk or posedge puc)
618
  if (puc)                       exec_jmp <= 1'b0;
619
  else if (inst_branch & decode) exec_jmp <= 1'b1;
620
  else if (e_state==`E_JUMP)     exec_jmp <= 1'b0;
621
 
622
reg exec_dst_wr;
623
always @(posedge mclk or posedge puc)
624
  if (puc)                     exec_dst_wr <= 1'b0;
625
  else if (e_state==`E_DST_RD) exec_dst_wr <= 1'b1;
626
  else if (e_state==`E_DST_WR) exec_dst_wr <= 1'b0;
627
 
628
reg exec_src_wr;
629
always @(posedge mclk or posedge puc)
630
  if (puc)                                               exec_src_wr <= 1'b0;
631
  else if (inst_type[`INST_SO] & (e_state==`E_SRC_RD))   exec_src_wr <= 1'b1;
632
  else if ((e_state==`E_SRC_WR) || (e_state==`E_DST_WR)) exec_src_wr <= 1'b0;
633
 
634
reg exec_dext_rdy;
635
always @(posedge mclk or posedge puc)
636
  if (puc)                     exec_dext_rdy <= 1'b0;
637
  else if (e_state==`E_DST_RD) exec_dext_rdy <= 1'b0;
638
  else if (inst_dext_rdy)      exec_dext_rdy <= 1'b1;
639
 
640
// Execution first state
641
//wire [3:0] e_first_state = dbg_halt_cmd        ? `E_IDLE   :
642
wire [3:0] e_first_state = ~dbg_halt_st  & inst_so_nxt[`IRQ] ? `E_IRQ_0  :
643
                            dbg_halt_cmd | (i_state==I_IDLE) ? `E_IDLE   :
644
                            cpuoff                           ? `E_IDLE   :
645
                            src_acalc_pre                    ? `E_SRC_AD :
646
                            src_rd_pre                       ? `E_SRC_RD :
647
                            dst_acalc_pre                    ? `E_DST_AD :
648
                            dst_rd_pre                       ? `E_DST_RD : `E_EXEC;
649
 
650
 
651
// State machine
652
//--------------------------------
653
 
654
// States Transitions
655
always @(e_state       or dst_acalc     or dst_rd   or inst_sext_rdy or
656
         inst_dext_rdy or exec_dext_rdy or exec_jmp or exec_dst_wr   or
657
         e_first_state or exec_src_wr)
658
    case(e_state)
659
      `E_IDLE   : e_state_nxt =  e_first_state;
660
      `E_IRQ_0  : e_state_nxt =  `E_IRQ_1;
661
      `E_IRQ_1  : e_state_nxt =  `E_IRQ_2;
662
      `E_IRQ_2  : e_state_nxt =  `E_IRQ_3;
663
      `E_IRQ_3  : e_state_nxt =  `E_IRQ_4;
664
      `E_IRQ_4  : e_state_nxt =  `E_EXEC;
665
 
666
      `E_SRC_AD : e_state_nxt =  inst_sext_rdy     ? `E_SRC_RD : `E_SRC_AD;
667
 
668
      `E_SRC_RD : e_state_nxt =  dst_acalc         ? `E_DST_AD :
669
                                 dst_rd            ? `E_DST_RD : `E_EXEC;
670
 
671
      `E_DST_AD : e_state_nxt =  (inst_dext_rdy |
672
                                 exec_dext_rdy)    ? `E_DST_RD : `E_DST_AD;
673
 
674
      `E_DST_RD : e_state_nxt =  `E_EXEC;
675
 
676
      `E_EXEC   : e_state_nxt =  exec_dst_wr       ? `E_DST_WR :
677
                                exec_jmp           ? `E_JUMP   :
678
                                exec_src_wr        ? `E_SRC_WR : e_first_state;
679
 
680
      `E_JUMP   : e_state_nxt =  e_first_state;
681
      `E_DST_WR : e_state_nxt =  exec_jmp           ? `E_JUMP   : e_first_state;
682
      `E_SRC_WR : e_state_nxt =  e_first_state;
683
      default  : e_state_nxt =  `E_IRQ_0;
684
    endcase
685
 
686
// State machine
687
always @(posedge mclk or posedge puc)
688
  if (puc)     e_state  <= `E_IRQ_1;
689
  else         e_state  <= e_state_nxt;
690
 
691
 
692
// Frontend State machine control signals
693
//----------------------------------------
694
 
695
wire exec_done = exec_jmp        ? (e_state==`E_JUMP)   :
696
                 exec_dst_wr     ? (e_state==`E_DST_WR) :
697
                 exec_src_wr     ? (e_state==`E_SRC_WR) : (e_state==`E_EXEC);
698
 
699
 
700
//=============================================================================
701
// 6)  EXECUTION-UNIT STATE CONTROL
702
//=============================================================================
703
 
704
//
705
// 6.1) ALU CONTROL SIGNALS
706
//-------------------------------------
707
//
708
// 12'b000000000001: Enable ALU source inverter
709
// 12'b000000000010: Enable Incrementer
710
// 12'b000000000100: Enable Incrementer on carry bit
711
// 12'b000000001000: Select Adder
712
// 12'b000000010000: Select AND
713
// 12'b000000100000: Select OR
714
// 12'b000001000000: Select XOR
715
// 12'b000010000000: Select DADD
716
// 12'b000100000000: Update N, Z & C (C=~Z)
717
// 12'b001000000000: Update all status bits
718
// 12'b010000000000: Update status bit for XOR instruction
719
// 12'b100000000000: Don't write to destination
720
 
721
reg  [11:0] inst_alu;
722
 
723
wire        alu_src_inv   = inst_to_nxt[`SUB]  | inst_to_nxt[`SUBC] |
724
                            inst_to_nxt[`CMP]  | inst_to_nxt[`BIC] ;
725
 
726
wire        alu_inc       = inst_to_nxt[`SUB]  | inst_to_nxt[`CMP];
727
 
728
wire        alu_inc_c     = inst_to_nxt[`ADDC] | inst_to_nxt[`DADD] |
729
                            inst_to_nxt[`SUBC];
730
 
731
wire        alu_add       = inst_to_nxt[`ADD]  | inst_to_nxt[`ADDC]       |
732
                            inst_to_nxt[`SUB]  | inst_to_nxt[`SUBC]       |
733
                            inst_to_nxt[`CMP]  | inst_type_nxt[`INST_JMP] |
734
                            inst_so_nxt[`RETI];
735
 
736
 
737
wire        alu_and       = inst_to_nxt[`AND]  | inst_to_nxt[`BIC]  |
738
                            inst_to_nxt[`BIT];
739
 
740
wire        alu_or        = inst_to_nxt[`BIS];
741
 
742
wire        alu_xor       = inst_to_nxt[`XOR];
743
 
744
wire        alu_dadd      = inst_to_nxt[`DADD];
745
 
746
wire        alu_stat_7    = inst_to_nxt[`BIT]  | inst_to_nxt[`AND]  |
747
                            inst_so_nxt[`SXT];
748
 
749
wire        alu_stat_f    = inst_to_nxt[`ADD]  | inst_to_nxt[`ADDC] |
750
                            inst_to_nxt[`SUB]  | inst_to_nxt[`SUBC] |
751
                            inst_to_nxt[`CMP]  | inst_to_nxt[`DADD] |
752
                            inst_to_nxt[`BIT]  | inst_to_nxt[`XOR]  |
753
                            inst_to_nxt[`AND]  |
754
                            inst_so_nxt[`RRC]  | inst_so_nxt[`RRA]  |
755
                            inst_so_nxt[`SXT];
756
 
757
wire        alu_shift     = inst_so_nxt[`RRC]  | inst_so_nxt[`RRA];
758
 
759
wire        exec_no_wr    = inst_to_nxt[`CMP] | inst_to_nxt[`BIT];
760
 
761
always @(posedge mclk or posedge puc)
762
  if (puc)         inst_alu <= 12'h000;
763
  else if (decode) inst_alu <= {exec_no_wr,
764
                                alu_shift,
765
                                alu_stat_f,
766
                                alu_stat_7,
767
                                alu_dadd,
768
                                alu_xor,
769
                                alu_or,
770
                                alu_and,
771
                                alu_add,
772
                                alu_inc_c,
773
                                alu_inc,
774
                                alu_src_inv};
775
 
776
 
777 34 olivier.girard
endmodule // omsp_frontend
778 33 olivier.girard
 
779 103 olivier.girard
`ifdef OMSP_NO_INCLUDE
780
`else
781 33 olivier.girard
`include "openMSP430_undefines.v"
782 103 olivier.girard
`endif

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