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olivier.girard |
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: ram.v
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//
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// *Module Description:
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// Scalable RAM model
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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`timescale 1ns / 100ps
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module ram (
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// OUTPUTs
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ram_dout, // RAM data output
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// INPUTs
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ram_addr, // RAM address
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ram_cen, // RAM chip enable (low active)
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ram_clk, // RAM clock
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ram_din, // RAM data input
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ram_wen // RAM write enable (low active)
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);
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// PARAMETERs
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//============
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parameter ADDR_MSB = 6;
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// OUTPUTs
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//============
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output [15:0] ram_dout; // RAM data output
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// INPUTs
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//============
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input [ADDR_MSB:0] ram_addr; // RAM address
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input ram_cen; // RAM chip enable (low active)
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input ram_clk; // RAM clock
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input [15:0] ram_din; // RAM data input
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input [1:0] ram_wen; // RAM write enable (low active)
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// RAM
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//============
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reg [15:0] mem [(1<<(ADDR_MSB+1))-1:0];
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reg [ADDR_MSB:0] ram_addr_reg;
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wire [15:0] mem_val = mem[ram_addr];
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always @(posedge ram_clk)
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if (~ram_cen)
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begin
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if (ram_wen==2'b00) mem[ram_addr] <= ram_din;
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else if (ram_wen==2'b01) mem[ram_addr] <= {ram_din[15:8], mem_val[7:0]};
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else if (ram_wen==2'b10) mem[ram_addr] <= {mem_val[15:8], ram_din[7:0]};
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ram_addr_reg <= ram_addr;
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end
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assign ram_dout = mem[ram_addr_reg];
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endmodule // ram
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