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// WARNING: Do NOT edit the input and output ports in this file in a text
2
// editor if you plan to continue editing the block that represents it in
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// the Block Editor! File corruption is VERY likely to occur.
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// Copyright (C) 1991-2003 Altera Corporation
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// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
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// support information,  device programming or simulation file,  and any other
8
// associated  documentation or information  provided by  Altera  or a partner
9
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
10
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
11
// other  use  of such  megafunction  design,  netlist,  support  information,
12
// device programming or simulation file,  or any other  related documentation
13
// or information  is prohibited  for  any  other purpose,  incrluding, but not
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// limited to  modification,  reverse engineering,  de-compiling, or use  with
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// any other  silicon devices,  unless such use is  explicitly  licensed under
16
// a separate agreement with  Altera  or a megafunction partner.  Title to the
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// intellectual property,  incrluding patents,  copyrights,  trademarks,  trade
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// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
19
// support  information,  device programming or simulation file,  or any other
20
// related documentation or information provided by  Altera  or a megafunction
21
// partner, remains with Altera, the megafunction partner, or their respective
22
// licensors. No other licenses, incrluding any licenses needed under any third
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// party's intellectual property, are provided herein.
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// Generated by Quartus II Version 2.2 (Build Build 176 02/04/2003)
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// Created on Tue May 13 14:49:34 2003
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//  Module Declaration
30
module iic_slave_3
31
(
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        // {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
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        scl, sda, send1, send2, send3, reset, rw, i2cadr1, i2cadr2, i2cadr3, slave_ack1, slave_ack2, slave_ack3, regout1, regout2, regout3, sreg, rd_clk1, rd_clk2, rd_clk3, wr_clk1, wr_clk2, wr_clk3, incr
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        // {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
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);
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// Port Declaration
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        // {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
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        input scl;
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        inout sda;
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        // busses for read transfer, slave --> master
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        input [7:0] send1;
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        input [7:0] send2;
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        input [7:0] send3;
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        input reset;
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        // read (1) or write (0) status
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        output rw;
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        // I2C address indicators
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        output i2cadr1;
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        output i2cadr2;
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        output i2cadr3;
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        // slave acknowledge
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        output slave_ack1;
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        output slave_ack2;
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        output slave_ack3;
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        // busses for write transfers, master --> slave
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        output [7:0] regout1;
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        output [7:0] regout2;
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        output [7:0] regout3;
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        // common shift register output 
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        output [7:0] sreg;
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        // read clock 
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        output rd_clk1;
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        output rd_clk2;
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        output rd_clk3;
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        // write clock 
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        output wr_clk1;
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        output wr_clk2;
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        output wr_clk3;
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        output incr; // counter output, not used
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72
        // {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
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// STATES
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parameter IDLE   = 3'b000;
75
parameter SLAVE  = 3'b001;
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parameter SL_ACK = 3'b010;
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parameter READ   = 3'b011;
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parameter RD_ACK = 3'b100;
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parameter WRITE  = 3'b101;
80
parameter WR_ACK = 3'b110;
81
parameter STOP   = 3'b111; // obsolete?
82
 
83
// IIC ADDRESS, edit to change
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parameter I2C_ADR1 = 7'b001_0000;       // h10, 1st address
85
parameter I2C_ADR2 = 7'b011_0100;       // h34, 2nd address
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parameter I2C_ADR3 = 7'b011_0101;       // h35, 3rd address
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88
reg sda;
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reg start;
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reg stop;
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reg slave_ack1;
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reg slave_ack2;
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reg slave_ack3;
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reg write_ack;
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wire read_ack;
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wire rw;
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reg [2:0] state;
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reg [3:0] bit_cnt;
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wire reset;
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reg incr;       // for external counters.
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reg [7:0] send; // temp 
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wire cnt4;
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wire cnt8;
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wire cnt9;
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wire this_adr1; // EQUAL
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wire this_adr2; // EQUAL
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wire this_adr3; // EQUAL
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wire sda_low;
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wire slave_ack_n;
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wire write_ack_n;
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wire load_send;
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wire [7:0] sreg; // for output  
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wire load;
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reg [8:0] sr;       // 9 bit shift register RECEIVE
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reg [7:0] sr_tx;    // 8 bit shift register SEND
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reg [7:0] regout1;               // output data #1
118
reg [7:0] regout2;               // output data #2
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reg [7:0] regout3;               // output data #3
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reg clear_rws;
122
reg read_pulse;
123
reg slave_pulse1;
124
reg slave_pulse2;
125
reg slave_pulse3;
126
reg write_pulse;
127
 
128
wire start_n;
129
wire stop_pulse;
130
wire sda_n;
131
wire stop_n;
132
wire scl_n;
133
wire count_bits;
134
wire read_TX;
135
wire stop_reset_n;
136
 
137
wire bit_zero;
138
wire reset_bit_cnt_n;
139
wire reset_start_n;
140
wire reset_stop_n;
141
// OUTPUT REG
142
        reg i2cadr1;
143
        reg i2cadr2;
144
        reg i2cadr3;
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146
wire reset_adress_n;
147
 
148
assign sda_n = ~sda;
149
assign scl_n = ~scl;
150
//assign sr_tx_out = sr_tx[7];
151
assign read_TX = state == READ ? ~sr_tx[7]: 1'b0;
152
 
153
//assign sda_low = ~read_ack && (slave_ack || write_ack || read_TX);
154
 
155
assign slave_ack_n = ~(slave_ack1 || slave_ack2 || slave_ack3);
156
assign write_ack_n = ~write_ack;        // sda_oe = 1, sda = 0
157
assign read_ack = (state == RD_ACK);    // sda_oe = 0, read ACK/NACK
158
assign this_adr1 = (sr[7:1] == I2C_ADR1) && cnt8;
159
assign this_adr2 = (sr[7:1] == I2C_ADR2) && cnt8;
160
assign this_adr3 = (sr[7:1] == I2C_ADR3) && cnt8;
161
 
162
//assign sda_low = slave_ack1 || slave_ack2 || slave_ack3 || write_ack || read_TX;
163
//assign sda = sda_low ? 1'b0 : 1'bz;
164
 
165
assign sreg = sr[7:0];
166
assign start_n = ~start;
167
 
168
assign wr_clk1 = state == WR_ACK && i2cadr1 && write_pulse ? 1'b1: 1'b0;
169
assign wr_clk2 = state == WR_ACK && i2cadr2 && write_pulse ? 1'b1: 1'b0;
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assign wr_clk3 = state == WR_ACK && i2cadr3 && write_pulse ? 1'b1: 1'b0;
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assign rd_clk1 = state == RD_ACK && i2cadr1 && read_pulse ? 1'b1: 1'b0;
172
assign rd_clk2 = state == RD_ACK && i2cadr2 && read_pulse ? 1'b1: 1'b0;
173
assign rd_clk3 = state == RD_ACK && i2cadr3 && read_pulse ? 1'b1: 1'b0;
174
//assign i2cadr1 = state == SLAVE ? this_adr1: i2cadr1;  // latch 
175
//assign i2cadr2 = state == SLAVE ? this_adr2: i2cadr2;  // latch 
176
//assign i2cadr3 = state == SLAVE ? this_adr3: i2cadr3;  // latch 
177
assign rw = (this_adr1 || this_adr2 || this_adr3) && (state == SLAVE)? sr[0]: rw; // latch
178
assign cnt4 = bit_cnt == 4'b0100;
179
assign cnt8 = bit_cnt == 4'b1000;
180
assign cnt9 = bit_cnt == 4'b1001;
181
assign bit_zero = bit_cnt == 4'b0000 ? 1'b0: 1'b1;
182
 
183
assign stop_n = ~stop;
184
assign count_bits = (state == SLAVE || state == READ || state == WRITE || state == RD_ACK || state == WR_ACK) ? 1'b1: 1'b0;
185
assign stop_reset_n = ~(stop || ~reset);
186
assign load_send = slave_ack1 || slave_ack2 || slave_ack3 || read_ack;
187
assign reset_bit_cnt_n = ~(stop || start || bit_cnt == 4'b1001);
188
assign reset_start_n = ~start;
189
assign reset_stop_n = ~stop;
190
assign reset_adress_n = ~(start || stop);
191
 
192
 
193
// SDA OUT
194
//assign sda_low = slave_ack1 || slave_ack2 || slave_ack3 || write_ack || read_TX;
195
//assign sda = sda_low ? 1'b0 : 1'bz;
196
 
197
always@(posedge scl_n or negedge reset_adress_n)
198
begin
199
        if(!reset_adress_n)
200
                sda = 1'bz;
201
        else if(slave_ack1 || slave_ack2 || slave_ack3 || write_ack || read_TX)
202
                sda = 1'b0;
203
        else
204
                sda = 1'bz;
205
end
206
 
207
// ADDRESS LATCH
208
always@(posedge scl_n or negedge reset_adress_n)
209
begin
210
        if(!reset_adress_n)
211
        begin
212
                i2cadr1 = 0;
213
                i2cadr2 = 0;
214
                i2cadr3 = 0;
215
        end
216
        else if(state == SLAVE)
217
        begin
218
                i2cadr1 = this_adr1;
219
                i2cadr2 = this_adr2;
220
                i2cadr3 = this_adr3;
221
        end
222
        else
223
        begin
224
                i2cadr1 = i2cadr1;
225
                i2cadr2 = i2cadr2;
226
                i2cadr3 = i2cadr3;
227
        end
228
end
229
 
230
// INCR EXT.
231
always@(posedge scl)
232
begin
233
        if((state == READ || state == WRITE) && cnt4)
234
                incr = 1'b1;
235
        else
236
                incr = 1'b0;
237
end
238
 
239
// MUX for send register
240
always@(i2cadr1 or i2cadr2 or i2cadr3 or send1 or send2 or send3)
241
begin
242
        casex({i2cadr1, i2cadr2, i2cadr3})
243
        3'b000: send = send; // latch?
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        3'b001: send = send3;
245
        3'b010: send = send2;
246
        3'b100: send = send1;
247
        endcase
248
end
249
 
250
// Shift register with load for output (I2C READ) #1
251
always @(negedge scl)
252
begin
253
        if(load_send)
254
                sr_tx = send;
255
        else
256
                sr_tx = {sr_tx[6:0], 1'b0};
257
end
258
 
259
// Shift register with load for input (I2C WRITE & ADDRESS)
260
always @(posedge scl)
261
begin
262
        sr = {sr[6:0], sda};
263
end
264
// Received data #1
265
always @(negedge scl)
266
begin
267
        if((state == WRITE) && cnt8 && i2cadr1)
268
        regout1 = sr[7:0];
269
end
270
 
271
// Received data #2
272
always @(negedge scl)
273
begin
274
        if((state == WRITE) && cnt8 && i2cadr2)
275
        regout2 = sr[7:0];
276
end
277
 
278
// Received data #3
279
always @(negedge scl)
280
begin
281
        if((state == WRITE) && cnt8 && i2cadr3)
282
        regout3 = sr[7:0];
283
end
284
 
285
// clear_rws
286
always@(posedge scl)
287
begin
288
        if(read_pulse || write_pulse || slave_pulse1 || slave_pulse2 || slave_pulse3)
289
                clear_rws = 1'b0;
290
        else
291
                clear_rws = 1'b1;
292
end
293
 
294
// read pulse
295
always@(posedge read_ack or negedge clear_rws)
296
begin
297
        if(!clear_rws)
298
                read_pulse = 1'b0;
299
        else
300
                read_pulse = 1'b1;
301
end
302
// slave pulse #1
303
always@(posedge slave_ack1 or negedge clear_rws)
304
begin
305
        if(!clear_rws)
306
                slave_pulse1 = 1'b0;
307
        else
308
                slave_pulse1 = 1'b1;
309
end
310
// slave pulse #2
311
always@(posedge slave_ack2 or negedge clear_rws)
312
begin
313
        if(!clear_rws)
314
                slave_pulse2 = 1'b0;
315
        else
316
                slave_pulse2 = 1'b1;
317
end
318
// slave pulse #3
319
always@(posedge slave_ack3 or negedge clear_rws)
320
begin
321
        if(!clear_rws)
322
                slave_pulse3 = 1'b0;
323
        else
324
                slave_pulse3 = 1'b1;
325
end
326
 
327
 
328
 
329
// write pulse
330
always@(posedge write_ack or negedge clear_rws)
331
begin
332
        if(!clear_rws)
333
                write_pulse = 1'b0;
334
        else
335
                write_pulse = 1'b1;
336
end
337
 
338
// bit counter
339
always@(posedge scl or negedge reset_bit_cnt_n)
340
begin
341
        if(!reset_bit_cnt_n)
342
                bit_cnt = 0;
343
        else
344
                bit_cnt = bit_cnt + 1'b1;
345
end
346
 
347
// slave acknowledge #1
348
always@(negedge scl)
349
begin
350
        if((state == SLAVE) && this_adr1) // && bit_cnt == 8
351
                slave_ack1 = 1'b1;
352
        else
353
                slave_ack1 = 1'b0;
354
end
355
// slave acknowledge #2
356
always@(negedge scl)
357
begin
358
        if((state == SLAVE) && this_adr2)
359
                slave_ack2 = 1'b1;
360
        else
361
                slave_ack2 = 1'b0;
362
end
363
// slave acknowledge #3
364
always@(negedge scl)
365
begin
366
        if((state == SLAVE) && this_adr3)
367
                slave_ack3 = 1'b1;
368
        else
369
                slave_ack3 = 1'b0;
370
end
371
 
372
 
373
// write acknowledge internal, always issued due to STATE MACHINE implementation.
374
always@(negedge scl)
375
begin
376
        if((state == WRITE) && cnt8)
377
                write_ack = 1'b1;
378
        else
379
                write_ack = 1'b0;
380
end
381
 
382
// START
383
always@(posedge sda_n or negedge reset_start_n)
384
begin
385
        if(!reset_start_n)
386
                start = 1'b0;
387
        else
388
                start = scl;
389
end
390
 
391
// STOP
392
always@(posedge sda or negedge reset_stop_n)
393
begin
394
        if(!reset_stop_n)
395
                stop = 1'b0;
396
        else
397
                stop = scl;
398
end
399
 
400
always@(posedge scl_n or negedge stop_reset_n or negedge start_n)
401
begin
402
        if(!stop_reset_n)
403
                state = IDLE;
404
        else if(!start_n)
405
                state = SLAVE;
406
        else
407
        begin
408
        case(state)
409
        IDLE:   begin if(start)                                                                 // 00
410
                        state = SLAVE;
411
                        else state = IDLE; end // dead end
412
        SLAVE:  begin if(bit_cnt < 8)                                                   // 01
413
                        state = SLAVE;
414
                        else if(this_adr1 || this_adr2 || this_adr3)
415
                        state = SL_ACK;
416
                        else state = IDLE; end
417
        SL_ACK: begin if(rw) state = READ;                                              // 02
418
                        else if(!rw) state = WRITE;
419
                        else state = IDLE; end
420
        READ:   begin if(bit_cnt < 8) state = READ;                             // 03
421
                        else state = RD_ACK; end
422
        RD_ACK: begin if(sr[0]) state = IDLE;                                    // 04   
423
                        else state = READ; end
424
        WRITE:  begin if(bit_cnt < 8) state = WRITE;                    // 05 
425
                        else state = WR_ACK; end
426
        WR_ACK: begin if(scl_n) state = IDLE;                                   // 05 
427
                        else state = WRITE; end                                                 // 06           
428
                //      else state = WRITE; end
429
        STOP:   begin state = IDLE; end                                                 // 07
430
        endcase
431
        end
432
end
433
 
434
endmodule

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