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[/] [ha1588/] [trunk/] [sim/] [top/] [ptp_drv_bfm/] [ptp_drv_bfm.c] - Blame information for rev 33

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Line No. Rev Author Line
1 21 edn_walter
#include <stdio.h>
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#include "svdpi.h"
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#include "../dpiheader.h"
5 33 edn_walter
 
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// define RTC address values
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#define RTC_CTRL            0x00000000
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#define RTC_NULL_0x4        0x00000004
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#define RTC_NULL_0x8        0x00000008
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#define RTC_NULL_0xC        0x0000000C
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#define RTC_TIME_SEC_H_LOAD 0x00000010
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#define RTC_TIME_SEC_L_LOAD 0x00000014
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#define RTC_TIME_NSC_H_LOAD 0x00000018
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#define RTC_TIME_NSC_L_LOAD 0x0000001C
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#define RTC_PERIOD_H_LOAD   0x00000020
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#define RTC_PERIOD_L_LOAD   0x00000024
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#define RTC_ACCMOD_H_LOAD   0x00000028
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#define RTC_ACCMOD_L_LOAD   0x0000002C
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#define RTC_ADJNUM_LOAD     0x00000030
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#define RTC_NULL_0x34       0x00000034
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#define RTC_ADJPER_H_LOAD   0x00000038
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#define RTC_ADJPER_L_LOAD   0x0000003C
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#define RTC_TIME_SEC_H_READ 0x00000040
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#define RTC_TIME_SEC_L_READ 0x00000044
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#define RTC_TIME_NSC_H_READ 0x00000048
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#define RTC_TIME_NSC_L_READ 0x0000004C
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// define RTC data values
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#define RTC_SET_CTRL_0 0x0
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#define RTC_GET_TIME   0x1
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#define RTC_SET_ADJ    0x2
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#define RTC_SET_PERIOD 0x4
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#define RTC_SET_TIME   0x8
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#define RTC_SET_RESET  0x10
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#define RTC_ACCMOD_H   0x3B9ACA00  // 1,000,000,000 for 30bit
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#define RTC_ACCMOD_L   0x0         // 256 for 8bit
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#define RTC_PERIOD_H   0x8  // 8ns for 125MHz rtc_clk
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#define RTC_PERIOD_L   0x0
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// define TSU address values
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#define TSU_CTRL         0x00000050
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#define TSU_RXQUE_STATUS 0x00000054
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#define TSU_TXQUE_STATUS 0x00000058
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#define TSU_NULL_0x5C    0x0000005C
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#define TSU_RXQUE_DATA_H 0x00000060
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#define TSU_RXQUE_DATA_L 0x00000064
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#define TSU_TXQUE_DATA_H 0x00000068
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#define TSU_TXQUE_DATA_L 0x0000006C
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// define TSU data values
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#define TSU_SET_CTRL_0 0x0
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#define TSU_GET_TXQUE  0x1
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#define TSU_GET_RXQUE  0x4
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#define TSU_SET_RESET  0xA
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54 21 edn_walter
int ptp_drv_bfm_c(double fw_delay)
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{
56 26 edn_walter
  unsigned int cpu_addr_i;
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  unsigned int cpu_data_i;
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  unsigned int cpu_data_o;
59 21 edn_walter
 
60 22 edn_walter
  // LOAD RTC PERIOD AND ACC_MODULO
61 33 edn_walter
  cpu_addr_i = RTC_PERIOD_H_LOAD;
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  cpu_data_i = RTC_PERIOD_H;
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  cpu_wr(cpu_addr_i, cpu_data_i);
64 33 edn_walter
  cpu_addr_i = RTC_PERIOD_L_LOAD;
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  cpu_data_i = RTC_PERIOD_L;
66 22 edn_walter
  cpu_wr(cpu_addr_i, cpu_data_i);
67 33 edn_walter
  cpu_addr_i = RTC_ACCMOD_H_LOAD;
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  cpu_data_i = RTC_ACCMOD_H;
69 22 edn_walter
  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = RTC_ACCMOD_L_LOAD;
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  cpu_data_i = RTC_ACCMOD_L;
72 22 edn_walter
  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = RTC_CTRL;
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  cpu_data_i = RTC_SET_CTRL_0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
76 33 edn_walter
  cpu_addr_i = RTC_CTRL;
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  cpu_data_i = RTC_SET_PERIOD;
78 22 edn_walter
  cpu_wr(cpu_addr_i, cpu_data_i);
79 33 edn_walter
  // RESET RTC AND TSU
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  cpu_addr_i = RTC_CTRL;
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  cpu_data_i = RTC_SET_CTRL_0;
82 22 edn_walter
  cpu_wr(cpu_addr_i, cpu_data_i);
83 33 edn_walter
  cpu_addr_i = RTC_CTRL;
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  cpu_data_i = RTC_SET_RESET;
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  cpu_wr(cpu_addr_i, cpu_data_i);
86 33 edn_walter
  cpu_addr_i = TSU_CTRL;
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  cpu_data_i = TSU_SET_CTRL_0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  cpu_addr_i = TSU_CTRL;
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  cpu_data_i = TSU_SET_RESET;
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  cpu_wr(cpu_addr_i, cpu_data_i);
92 26 edn_walter
  // READ RTC SEC AND NS
93 33 edn_walter
  cpu_addr_i = RTC_CTRL;
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  cpu_data_i = RTC_SET_CTRL_0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
96 33 edn_walter
  cpu_addr_i = RTC_CTRL;
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  cpu_data_i = RTC_GET_TIME;
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  cpu_wr(cpu_addr_i, cpu_data_i);
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  do {
100 33 edn_walter
    cpu_addr_i = RTC_CTRL;
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    cpu_rd(cpu_addr_i, &cpu_data_o);
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    //printf("%08x\n", (cpu_data_o & 0x1));
103 33 edn_walter
  } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
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  cpu_addr_i = RTC_TIME_SEC_H_READ;
105 26 edn_walter
  cpu_rd(cpu_addr_i, &cpu_data_o);
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  printf("\ntime: \n%08x\n", cpu_data_o);
107 33 edn_walter
  cpu_addr_i = RTC_TIME_SEC_L_READ;
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  cpu_rd(cpu_addr_i, &cpu_data_o);
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  printf("%08x\n", cpu_data_o);
110 33 edn_walter
  cpu_addr_i = RTC_TIME_NSC_H_READ;
111 26 edn_walter
  cpu_rd(cpu_addr_i, &cpu_data_o);
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  printf("%08x\n", cpu_data_o);
113 33 edn_walter
  cpu_addr_i = RTC_TIME_NSC_L_READ;
114 26 edn_walter
  cpu_rd(cpu_addr_i, &cpu_data_o);
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  printf("%08x\n", cpu_data_o);
116 22 edn_walter
  // LOAD RTC SEC AND NS
117 33 edn_walter
  cpu_addr_i = RTC_TIME_SEC_H_LOAD;
118 22 edn_walter
  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
120 33 edn_walter
  cpu_addr_i = RTC_TIME_SEC_L_LOAD;
121 22 edn_walter
  cpu_data_i = 0x1;
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  cpu_wr(cpu_addr_i, cpu_data_i);
123 33 edn_walter
  cpu_addr_i = RTC_TIME_NSC_H_LOAD;
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  cpu_data_i = RTC_ACCMOD_H - 0xA;
125 22 edn_walter
  cpu_wr(cpu_addr_i, cpu_data_i);
126 33 edn_walter
  cpu_addr_i = RTC_TIME_NSC_L_LOAD;
127 22 edn_walter
  cpu_data_i = 0x0;
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  cpu_wr(cpu_addr_i, cpu_data_i);
129 33 edn_walter
  cpu_addr_i = RTC_CTRL;
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  cpu_data_i = RTC_SET_CTRL_0;
131 22 edn_walter
  cpu_wr(cpu_addr_i, cpu_data_i);
132 33 edn_walter
  cpu_addr_i = RTC_CTRL;
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  cpu_data_i = RTC_SET_TIME;
134 22 edn_walter
  cpu_wr(cpu_addr_i, cpu_data_i);
135
  // LOAD RTC ADJ
136 33 edn_walter
  cpu_addr_i = RTC_ADJNUM_LOAD;
137 22 edn_walter
  cpu_data_i = 0x100;
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  cpu_wr(cpu_addr_i, cpu_data_i);
139 33 edn_walter
  cpu_addr_i = RTC_ADJPER_H_LOAD;
140 22 edn_walter
  cpu_data_i = 0x1;
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  cpu_wr(cpu_addr_i, cpu_data_i);
142 33 edn_walter
  cpu_addr_i = RTC_ADJPER_L_LOAD;
143 22 edn_walter
  cpu_data_i = 0x20;
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  cpu_wr(cpu_addr_i, cpu_data_i);
145 33 edn_walter
  cpu_addr_i = RTC_CTRL;
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  cpu_data_i = RTC_SET_CTRL_0;
147 23 edn_walter
  cpu_wr(cpu_addr_i, cpu_data_i);
148 33 edn_walter
  cpu_addr_i = RTC_CTRL;
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  cpu_data_i = RTC_SET_ADJ;
150 22 edn_walter
  cpu_wr(cpu_addr_i, cpu_data_i);
151 23 edn_walter
  // READ RTC SEC AND NS
152 33 edn_walter
  cpu_addr_i = RTC_CTRL;
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  cpu_data_i = RTC_SET_CTRL_0;
154 22 edn_walter
  cpu_wr(cpu_addr_i, cpu_data_i);
155 33 edn_walter
  cpu_addr_i = RTC_CTRL;
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  cpu_data_i = RTC_GET_TIME;
157 22 edn_walter
  cpu_wr(cpu_addr_i, cpu_data_i);
158 24 edn_walter
  do {
159 33 edn_walter
    cpu_addr_i = RTC_CTRL;
160 24 edn_walter
    cpu_rd(cpu_addr_i, &cpu_data_o);
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    //printf("%08x\n", (cpu_data_o & 0x1));
162 33 edn_walter
  } while ((cpu_data_o & RTC_GET_TIME) == 0x0);
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  cpu_addr_i = RTC_TIME_SEC_H_READ;
164 23 edn_walter
  cpu_rd(cpu_addr_i, &cpu_data_o);
165 26 edn_walter
  printf("\ntime: \n%08x\n", cpu_data_o);
166 33 edn_walter
  cpu_addr_i = RTC_TIME_SEC_L_READ;
167 23 edn_walter
  cpu_rd(cpu_addr_i, &cpu_data_o);
168 26 edn_walter
  printf("%08x\n", cpu_data_o);
169 33 edn_walter
  cpu_addr_i = RTC_TIME_NSC_H_READ;
170 23 edn_walter
  cpu_rd(cpu_addr_i, &cpu_data_o);
171 26 edn_walter
  printf("%08x\n", cpu_data_o);
172 33 edn_walter
  cpu_addr_i = RTC_TIME_NSC_L_READ;
173 23 edn_walter
  cpu_rd(cpu_addr_i, &cpu_data_o);
174 26 edn_walter
  printf("%08x\n", cpu_data_o);
175 22 edn_walter
 
176 24 edn_walter
  int i;
177 33 edn_walter
  int rx_queue_num;
178
  int tx_queue_num;
179
  while (1) {
180 24 edn_walter
  // POLL TSU RX STATUS
181 33 edn_walter
  cpu_addr_i = TSU_RXQUE_STATUS;
182
  cpu_rd(cpu_addr_i, &cpu_data_o);
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  rx_queue_num = cpu_data_o;
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  //printf("%08x\n", rx_queue_num);
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  if (rx_queue_num > 0x0) {
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    // READ TSU RX FIFO
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    for (i=rx_queue_num; i>0; i--) {
188
      cpu_addr_i = TSU_CTRL;
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      cpu_data_i = TSU_SET_CTRL_0;
190 24 edn_walter
      cpu_wr(cpu_addr_i, cpu_data_i);
191 33 edn_walter
      cpu_addr_i = TSU_CTRL;
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      cpu_data_i = TSU_GET_RXQUE;
193 24 edn_walter
      cpu_wr(cpu_addr_i, cpu_data_i);
194 31 edn_walter
      do {
195 33 edn_walter
        cpu_addr_i = TSU_CTRL;
196 31 edn_walter
        cpu_rd(cpu_addr_i, &cpu_data_o);
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        //printf("%08x\n", (cpu_data_o & 0x1));
198 33 edn_walter
      } while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
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      cpu_addr_i = TSU_RXQUE_DATA_H;
200 24 edn_walter
      cpu_rd(cpu_addr_i, &cpu_data_o);
201 26 edn_walter
      printf("\nRx stamp: \n%08x\n", cpu_data_o);
202 33 edn_walter
      cpu_addr_i = TSU_RXQUE_DATA_L;
203 24 edn_walter
      cpu_rd(cpu_addr_i, &cpu_data_o);
204 26 edn_walter
      printf("%08x\n", cpu_data_o);
205 33 edn_walter
    }
206 24 edn_walter
  }
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  // POLL TSU TX STATUS
208 33 edn_walter
  cpu_addr_i = TSU_TXQUE_STATUS;
209
  cpu_rd(cpu_addr_i, &cpu_data_o);
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  tx_queue_num = cpu_data_o;
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  //printf("%08x\n", tx_queue_num);
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  if (tx_queue_num > 0x0) {
213
    // READ TSU TX FIFO
214
    for (i=tx_queue_num; i>0; i--) {
215
      cpu_addr_i = TSU_CTRL;
216
      cpu_data_i = TSU_SET_CTRL_0;
217 24 edn_walter
      cpu_wr(cpu_addr_i, cpu_data_i);
218 33 edn_walter
      cpu_addr_i = TSU_CTRL;
219
      cpu_data_i = TSU_GET_TXQUE;
220 24 edn_walter
      cpu_wr(cpu_addr_i, cpu_data_i);
221 31 edn_walter
      do {
222 33 edn_walter
        cpu_addr_i = TSU_CTRL;
223 31 edn_walter
        cpu_rd(cpu_addr_i, &cpu_data_o);
224
        //printf("%08x\n", (cpu_data_o & 0x1));
225 33 edn_walter
      } while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
226
      cpu_addr_i = TSU_TXQUE_DATA_H;
227 24 edn_walter
      cpu_rd(cpu_addr_i, &cpu_data_o);
228 26 edn_walter
      printf("\nTx stamp: \n%08x\n", cpu_data_o);
229 33 edn_walter
      cpu_addr_i = TSU_TXQUE_DATA_L;
230 24 edn_walter
      cpu_rd(cpu_addr_i, &cpu_data_o);
231 26 edn_walter
      printf("%08x\n", cpu_data_o);
232 33 edn_walter
    }
233 24 edn_walter
  }
234 33 edn_walter
  }
235 24 edn_walter
 
236 22 edn_walter
  // READ BACK ALL REGISTERS
237
  for (;;)
238 21 edn_walter
  {
239 22 edn_walter
    int t;
240
    for (t=0; t<=0x5c; t=t+4)
241
    {
242 24 edn_walter
      cpu_hd(10);
243
 
244 22 edn_walter
      cpu_addr_i = t;
245 21 edn_walter
      cpu_rd(cpu_addr_i, &cpu_data_o);
246 22 edn_walter
    }
247 21 edn_walter
  }
248
 
249
  return(0); /* Return success (required by tasks) */
250
}

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