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[/] [ha1588/] [trunk/] [sim/] [top/] [ha1588_tb.v] - Blame information for rev 32

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Line No. Rev Author Line
1 21 edn_walter
`timescale 1ns/1ns
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module ha1588_tb ();
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reg up_clk;
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wire up_wr, up_rd;
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wire [ 7:0] up_addr;
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wire [31:0] up_data_wr, up_data_rd;
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initial begin
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             up_clk = 1'b0;
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  forever #5 up_clk = !up_clk;
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end
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reg rtc_clk;
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initial begin
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             rtc_clk = 1'b0;
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  forever #4 rtc_clk = !rtc_clk;
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end
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reg rst;
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initial begin
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      rst = 1'b1;
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  #10 rst = 1'b0;
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end
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26 24 edn_walter
wire        rx_gmii_clk;
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wire        rx_gmii_ctrl;
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wire [ 7:0] rx_gmii_data;
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wire        tx_gmii_clk;
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wire        tx_gmii_ctrl;
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wire [ 7:0] tx_gmii_data;
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gmii_rx_bfm NIC_DRV_RX_BFM (
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  .gmii_rxclk(rx_gmii_clk),
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  .gmii_rxctrl(rx_gmii_ctrl),
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  .gmii_rxdata(rx_gmii_data)
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);
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gmii_tx_bfm NIC_DRV_TX_BFM (
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  .gmii_txclk(tx_gmii_clk),
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  .gmii_txctrl(tx_gmii_ctrl),
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  .gmii_txdata(tx_gmii_data)
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);
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45 21 edn_walter
ptp_drv_bfm_sv PTP_DRV_BFM (
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  .up_clk(up_clk),
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  .up_wr(up_wr),
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  .up_rd(up_rd),
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  .up_addr(up_addr),
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  .up_data_wr(up_data_wr),
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  .up_data_rd(up_data_rd)
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);
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54 24 edn_walter
ha1588 PTP_HA_DUT (
55 21 edn_walter
  .rst(rst),
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  .clk(up_clk),
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  .wr_in(up_wr),
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  .rd_in(up_rd),
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  .addr_in(up_addr),
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  .data_in(up_data_wr),
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  .data_out(up_data_rd),
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  .rtc_clk(rtc_clk),
64 32 edn_walter
  .rtc_time_ptp_ns(),
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  .rtc_time_ptp_sec(),
66 21 edn_walter
 
67 24 edn_walter
  .rx_gmii_clk(rx_gmii_clk),
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  .rx_gmii_ctrl(rx_gmii_ctrl),
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  .rx_gmii_data(rx_gmii_data),
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  .tx_gmii_clk(tx_gmii_clk),
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  .tx_gmii_ctrl(tx_gmii_ctrl),
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  .tx_gmii_data(tx_gmii_data)
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);
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initial begin
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        ha1588_tb.PTP_DRV_BFM.up_start = 1;
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        #100000000 $stop;
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end
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endmodule

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