OpenCores

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [sim/] [top/] [ha1588_tb.v] - Blame information for rev 21

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 21 edn_walter
`timescale 1ns/1ns
2
 
3
module ha1588_tb ();
4
 
5
reg up_clk;
6
wire up_wr, up_rd;
7
wire [ 7:0] up_addr;
8
wire [31:0] up_data_wr, up_data_rd;
9
initial begin
10
             up_clk = 1'b0;
11
  forever #5 up_clk = !up_clk;
12
end
13
 
14
reg rtc_clk;
15
initial begin
16
             rtc_clk = 1'b0;
17
  forever #4 rtc_clk = !rtc_clk;
18
end
19
 
20
reg rst;
21
initial begin
22
      rst = 1'b1;
23
  #10 rst = 1'b0;
24
end
25
 
26
ptp_drv_bfm_sv PTP_DRV_BFM (
27
  .up_clk(up_clk),
28
  .up_wr(up_wr),
29
  .up_rd(up_rd),
30
  .up_addr(up_addr),
31
  .up_data_wr(up_data_wr),
32
  .up_data_rd(up_data_rd)
33
);
34
 
35
ha1588 PTP_HA_DUT(
36
  .rst(rst),
37
  .clk(up_clk),
38
  .wr_in(up_wr),
39
  .rd_in(up_rd),
40
  .addr_in(up_addr),
41
  .data_in(up_data_wr),
42
  .data_out(up_data_rd),
43
 
44
  .rtc_clk(rtc_clk),
45
 
46
  .rx_gmii_clk(),
47
  .rx_gmii_ctrl(),
48
  .rx_gmii_data(),
49
  .tx_gmii_clk(),
50
  .tx_gmii_ctrl(),
51
  .tx_gmii_data()
52
);
53
 
54
initial begin
55
        ha1588_tb.PTP_DRV_BFM.up_start = 1;
56
        #100000000 $stop;
57
end
58
 
59
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.