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[/] [ha1588/] [trunk/] [rtl/] [tsu/] [tsu.v] - Blame information for rev 15

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Line No. Rev Author Line
1 4 ash_riple
`timescale 1ns/1ns
2
 
3 15 edn_walter
module tsu (
4 4 ash_riple
    input       rst,
5
 
6
    input       gmii_clk,
7
    input       gmii_ctrl,
8
    input [7:0] gmii_data,
9
 
10
    input        rtc_timer_clk,
11 9 edn_walter
    input [31:0] rtc_timer_in,
12 4 ash_riple
 
13
    input         q_rst,
14 5 ash_riple
    input         q_rd_clk,
15 4 ash_riple
    input         q_rd_en,
16
    output [ 7:0] q_rd_stat,
17 9 edn_walter
    output [55:0] q_rd_data
18 4 ash_riple
);
19
 
20
// buffer gmii input
21
reg       int_gmii_ctrl;
22
reg       int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4, int_gmii_ctrl_d5;
23
reg [7:0] int_gmii_data;
24
reg [7:0] int_gmii_data_d1;
25
always @(posedge rst or posedge gmii_clk) begin
26
  if (rst) begin
27
    int_gmii_ctrl    <= 1'b0;
28
    int_gmii_ctrl_d1 <= 1'b0;
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    int_gmii_ctrl_d2 <= 1'b0;
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    int_gmii_ctrl_d3 <= 1'b0;
31
    int_gmii_ctrl_d4 <= 1'b0;
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    int_gmii_ctrl_d5 <= 1'b0;
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    int_gmii_data    <= 8'h00;
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    int_gmii_data_d1 <= 8'h00;
35
  end
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  else begin
37
    int_gmii_ctrl    <= gmii_ctrl;
38
    int_gmii_ctrl_d1 <= int_gmii_ctrl;
39
    int_gmii_ctrl_d2 <= int_gmii_ctrl_d1;
40
    int_gmii_ctrl_d3 <= int_gmii_ctrl_d2;
41
    int_gmii_ctrl_d4 <= int_gmii_ctrl_d3;
42
    int_gmii_ctrl_d5 <= int_gmii_ctrl_d4;
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    int_gmii_data    <= gmii_data;
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    int_gmii_data_d1 <= int_gmii_data;
45
  end
46
end
47
 
48
// ptp CDC time stamping
49
wire ts_req = int_gmii_ctrl;
50
reg  ts_req_d1, ts_req_d2, ts_req_d3;
51
always @(posedge rst or posedge rtc_timer_clk) begin
52
  if (rst) begin
53
    ts_req_d1 <= 1'b0;
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    ts_req_d2 <= 1'b0;
55
    ts_req_d3 <= 1'b0;
56
  end
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  else begin
58
    ts_req_d1 <= ts_req;
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    ts_req_d2 <= ts_req_d1;
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    ts_req_d3 <= ts_req_d2;
61
  end
62
end
63 9 edn_walter
reg [31:0] rtc_time_stamp;
64 4 ash_riple
always @(posedge rst or posedge rtc_timer_clk) begin
65
  if (rst)
66 9 edn_walter
    rtc_time_stamp <= 32'd0;
67 4 ash_riple
  else
68
    if (ts_req_d2 & !ts_req_d3)
69
      rtc_time_stamp <= rtc_timer_in;
70
end
71
reg ts_ack, ts_ack_clr;
72
always @(posedge ts_ack_clr or posedge rtc_timer_clk) begin
73
  if (ts_ack_clr)
74
    ts_ack <= 1'b0;
75
  else
76
    if (ts_req_d2 & !ts_req_d3)
77
      ts_ack <= 1'b1;
78
end
79
 
80
reg ts_ack_d1, ts_ack_d2, ts_ack_d3;
81
always @(posedge rst or posedge gmii_clk) begin
82
  if (rst) begin
83
    ts_ack_d1 <= 1'b0;
84
    ts_ack_d2 <= 1'b0;
85
    ts_ack_d3 <= 1'b0;
86
  end
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  else begin
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    ts_ack_d1 <= ts_ack;
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    ts_ack_d2 <= ts_ack_d1;
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    ts_ack_d3 <= ts_ack_d2;
91
  end
92
end
93 9 edn_walter
reg [31:0] gmii_time_stamp;
94 4 ash_riple
always @(posedge rst or posedge gmii_clk) begin
95
  if (rst) begin
96 9 edn_walter
    gmii_time_stamp <= 32'd0;
97 4 ash_riple
    ts_ack_clr      <= 1'b0;
98
  end
99
  else begin
100
    if (ts_ack_d2 & !ts_ack_d3) begin
101
      gmii_time_stamp <= rtc_time_stamp;
102
      ts_ack_clr      <= 1'b1;
103
    end
104
    else begin
105
      gmii_time_stamp <= gmii_time_stamp;
106
      ts_ack_clr      <= 1'b0;
107
    end
108
  end
109
end
110
 
111
// 8b-32b datapath gearbox
112
reg        int_valid;
113
reg        int_sop, int_eop;
114
reg [ 1:0] int_bcnt, int_mod;
115
reg [31:0] int_data;
116
always @(posedge rst or posedge gmii_clk) begin
117
  if (rst)
118
    int_bcnt <= 2'd0;
119
  else
120
    if (int_gmii_ctrl_d1 | (int_bcnt!=2'd0))
121
      int_bcnt <= int_bcnt + 2'd1;
122
    else
123
      int_bcnt <= 2'd0;
124
end
125
always @(posedge rst or posedge gmii_clk) begin
126
  if (rst) begin
127
    int_data  <= 32'd0;
128
    int_valid <=  1'b0;
129
    int_mod   <=  2'd0;
130
  end
131
  else begin
132
    if (int_gmii_ctrl_d1) begin
133
      int_data[ 7: 0] <= (int_bcnt==2'd3)? int_gmii_data_d1:int_data[ 7: 0];
134
      int_data[15: 8] <= (int_bcnt==2'd2)? int_gmii_data_d1:int_data[15: 8];
135
      int_data[23:16] <= (int_bcnt==2'd1)? int_gmii_data_d1:int_data[23:16];
136
      int_data[31:24] <= (int_bcnt==2'd0)? int_gmii_data_d1:int_data[31:24];
137
    end
138
 
139
    if (int_bcnt==2'd3)
140
      int_valid <= 1'b1;
141
    else
142
      int_valid <= 1'b0;
143
 
144
    if (int_gmii_ctrl_d1 & !int_gmii_ctrl_d2)
145
      int_mod <= 2'd0;
146
    else if (!int_gmii_ctrl_d1 & int_gmii_ctrl_d2)
147
      int_mod <= int_bcnt;
148
 
149
    if (int_gmii_ctrl & !int_gmii_ctrl_d5 & int_bcnt==2'd3)
150
      int_sop <= 1'b1;
151
    else
152
      int_sop <= 1'b0;
153
 
154
    if (!int_gmii_ctrl & int_bcnt==2'd3)
155
      int_eop <= 1'b1;
156
    else
157
      int_eop <= 1'b0;
158
 
159
  end
160
end
161
 
162
// ptp packet parser here
163
// works at 1/4 gmii_clk frequency, needs multicycle timing constraint
164
wire        ptp_found;
165 9 edn_walter
wire [51:0] ptp_infor;
166 4 ash_riple
ptp_parser parser(
167
  .clk(gmii_clk),
168
  .rst(rst),
169 10 edn_walter
  .int_data(int_data),
170
  .int_valid(int_valid),
171
  .int_sop(int_sop),
172
  .int_eop(int_eop),
173
  .int_mod(int_mod),
174
  .sop_time(gmii_time_stamp),
175 4 ash_riple
  .ptp_found(ptp_found),
176
  .ptp_infor(ptp_infor)
177
);
178
 
179
// ptp time stamp dcfifo
180 5 ash_riple
wire q_wr_clk = gmii_clk;
181
wire q_wr_en = ptp_found;
182 9 edn_walter
wire [55:0] q_wr_data = {4'd0, ptp_infor};
183 7 edn_walter
wire [3:0] q_wrusedw;
184
wire [3:0] q_rdusedw;
185 4 ash_riple
 
186 5 ash_riple
ptp_queue queue(
187
  .aclr(q_rst),
188
 
189
  .wrclk(q_wr_clk),
190 7 edn_walter
  .wrreq(q_wr_en && q_wrusedw<=15),
191 5 ash_riple
  .data(q_wr_data),
192
  .wrusedw(q_wrusedw),
193
 
194
  .rdclk(q_rd_clk),
195
  .rdreq(q_rd_en && q_rdusedw>=1),
196
  .q(q_rd_data),
197
  .rdusedw(q_rdusedw)
198
);
199
 
200 7 edn_walter
assign q_rd_stat = {4'd0, q_rdusedw};
201 5 ash_riple
 
202 4 ash_riple
endmodule

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