OpenCores

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [rtl/] [top/] [ha1588.v] - Blame information for rev 30

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 18 edn_walter
`timescale 1ns/1ns
2
 
3
module ha1588 (
4
  input         rst,clk,
5
  input         wr_in,rd_in,
6 21 edn_walter
  input  [ 7:0] addr_in,
7 18 edn_walter
  input  [31:0] data_in,
8
  output [31:0] data_out,
9
 
10
  input rtc_clk,
11
 
12
  input       rx_gmii_clk,
13
  input       rx_gmii_ctrl,
14
  input [7:0] rx_gmii_data,
15
  input       tx_gmii_clk,
16
  input       tx_gmii_ctrl,
17
  input [7:0] tx_gmii_data
18
);
19
 
20
wire rtc_rst;
21
wire rtc_time_ld, rtc_period_ld, rtc_adj_ld;
22
wire [37:0] rtc_time_reg_ns;
23
wire [47:0] rtc_time_reg_sec;
24
wire [39:0] rtc_period;
25
wire [37:0] rtc_time_acc_modulo;
26
wire [31:0] rtc_adj_ld_data;
27
wire [39:0] rtc_period_adj;
28
wire [37:0] rtc_time_reg_ns_val;
29
wire [47:0] rtc_time_reg_sec_val;
30 30 edn_walter
wire [35:0] rtc_time_reg_val = {rtc_time_reg_sec_val[3:0], 2'b00, rtc_time_reg_ns_val[37:8]};  // 16.000,000,000 sec
31 18 edn_walter
 
32
wire rx_q_rst, rx_q_clk;
33
wire rx_q_rd_en;
34
wire [ 7:0] rx_q_stat;
35 27 edn_walter
wire [63:0] rx_q_data;
36 18 edn_walter
wire tx_q_rst, tx_q_clk;
37
wire tx_q_rd_en;
38
wire [ 7:0] tx_q_stat;
39 27 edn_walter
wire [63:0] tx_q_data;
40 18 edn_walter
 
41
rgs u_rgs
42
(
43
  .rst(rst),
44
  .clk(clk),
45
  .wr_in(wr_in),
46
  .rd_in(rd_in),
47
  .addr_in(addr_in),
48
  .data_in(data_in),
49
  .data_out(data_out),
50
  .rtc_clk_in(rtc_clk),
51
  .rtc_rst_out(rtc_rst),
52
  .time_ld_out(rtc_time_ld),
53
  .time_reg_ns_out(rtc_time_reg_ns),
54
  .time_reg_sec_out(rtc_time_reg_sec),
55
  .period_ld_out(rtc_period_ld),
56
  .period_out(rtc_period),
57
  .time_acc_modulo_out(rtc_time_acc_modulo),
58
  .adj_ld_out(rtc_adj_ld),
59
  .adj_ld_data_out(rtc_adj_ld_data),
60
  .period_adj_out(rtc_period_adj),
61
  .time_reg_ns_in(rtc_time_reg_ns_val),
62
  .time_reg_sec_in(rtc_time_reg_sec_val),
63
  .rx_q_rst_out(rx_q_rst),
64
  .rx_q_rd_clk_out(rx_q_clk),
65
  .rx_q_rd_en_out(rx_q_rd_en),
66
  .rx_q_stat_in(rx_q_stat),
67
  .rx_q_data_in(rx_q_data),
68
  .tx_q_rst_out(tx_q_rst),
69
  .tx_q_rd_clk_out(tx_q_clk),
70
  .tx_q_rd_en_out(tx_q_rd_en),
71
  .tx_q_stat_in(tx_q_stat),
72
  .tx_q_data_in(tx_q_data)
73
);
74
 
75
rtc u_rtc
76
(
77
  .rst(rtc_rst),
78
  .clk(rtc_clk),
79
  .time_ld(rtc_time_ld),
80
  .time_reg_ns_in(rtc_time_reg_ns),
81
  .time_reg_sec_in(rtc_time_reg_sec),
82
  .period_ld(rtc_period_ld),
83
  .period_in(rtc_period),
84
  .time_acc_modulo(rtc_time_acc_modulo),
85
  .adj_ld(rtc_adj_ld),
86
  .adj_ld_data(rtc_adj_ld_data),
87
  .period_adj(rtc_period_adj),
88
  .time_reg_ns(rtc_time_reg_ns_val),
89
  .time_reg_sec(rtc_time_reg_sec_val)
90
);
91
 
92
tsu u_rx_tsu
93
(
94
  .rst(rst),
95
  .gmii_clk(rx_gmii_clk),
96
  .gmii_ctrl(rx_gmii_ctrl),
97
  .gmii_data(rx_gmii_data),
98
  .rtc_timer_clk(rtc_clk),
99
  .rtc_timer_in(rtc_time_reg_val),
100
  .q_rst(rx_q_rst),
101
  .q_rd_clk(rx_q_clk),
102
  .q_rd_en(rx_q_rd_en),
103
  .q_rd_stat(rx_q_stat),
104
  .q_rd_data(rx_q_data)
105
);
106
 
107
tsu u_tx_tsu
108
(
109
  .rst(rst),
110
  .gmii_clk(tx_gmii_clk),
111
  .gmii_ctrl(tx_gmii_ctrl),
112
  .gmii_data(tx_gmii_data),
113
  .rtc_timer_clk(rtc_clk),
114
  .rtc_timer_in(rtc_time_reg_val),
115
  .q_rst(tx_q_rst),
116
  .q_rd_clk(tx_q_clk),
117
  .q_rd_en(tx_q_rd_en),
118
  .q_rd_stat(tx_q_stat),
119
  .q_rd_data(tx_q_data)
120
);
121
 
122
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.