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[/] [ha1588/] [trunk/] [rtl/] [rtc/] [rtc.v] - Blame information for rev 45

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1 34 edn_walter
/*
2 38 edn_walter
 * rtc.v
3 34 edn_walter
 *
4 37 edn_walter
 * Copyright (c) 2012, BABY&HW. All rights reserved.
5 34 edn_walter
 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2.1 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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 * MA 02110-1301  USA
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 */
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22 3 ash_riple
`timescale 1ns/1ns
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24 15 edn_walter
module rtc (
25 3 ash_riple
  input rst, clk,
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  // 1. direct time adjustment: ToD set up
27 39 edn_walter
  input        time_ld,
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  input [37:0] time_reg_ns_in,   // 37:8 ns, 7:0 ns_fraction
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  input [47:0] time_reg_sec_in,  // 47:0 sec
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  // 2. frequency adjustment: frequency set up for drift compensation
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  input        period_ld,
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  input [39:0] period_in,        // 39:32 ns, 31:0 ns_fraction
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  // 3. precise time adjustment: small time difference adjustment with a time mark
34 39 edn_walter
  input        adj_ld,
35 3 ash_riple
  input [31:0] adj_ld_data,
36 38 edn_walter
  output reg   adj_ld_done,
37 3 ash_riple
  input [39:0] period_adj,  // 39:32 ns, 31:0 ns_fraction
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39 32 edn_walter
  // time output: for internal with ns fraction
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  output [37:0] time_reg_ns,  // 37:8 ns, 7:0 ns_fraction
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  output [47:0] time_reg_sec, // 47:0 sec
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  // time output: for external with ptp standard
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  output [31:0] time_ptp_ns,  // 31:0 ns
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  output [47:0] time_ptp_sec  // 47:0 sec
45 3 ash_riple
);
46
 
47 38 edn_walter
parameter time_acc_modulo = 38'd256000000000;
48
 
49 3 ash_riple
reg  [39:0] period_fix;  // 39:32 ns, 31:0 ns_fraction
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reg  [31:0] adj_cnt;
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reg  [39:0] time_adj;    // 39:32 ns, 31:0 ns_fraction
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// frequency and small time difference adjustment registers
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always @(posedge rst or posedge clk) begin
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  if (rst) begin
55 38 edn_walter
    period_fix  <= period_fix;  //40'd0;
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    adj_cnt     <= 32'hffffffff;
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    time_adj    <= time_adj;    //40'd0;
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    adj_ld_done <= 1'b0;
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  end
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  else begin
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    if (period_ld)  // load period adjustment
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      period_fix <= period_in;
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    else
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      period_fix <= period_fix;
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    if (adj_ld)  // load precise time adjustment time mark
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      adj_cnt  <= adj_ld_data;
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    else if (adj_cnt==32'hffffffff)
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      adj_cnt  <= adj_cnt;  // no cycling
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    else
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      adj_cnt  <= adj_cnt - 1;  // counting down
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    if (adj_cnt==0)  // change period temparorily
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      time_adj <= period_fix + period_adj;
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    else
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      time_adj <= period_fix + 0;
77 38 edn_walter
 
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    if (adj_cnt==32'hffffffff)
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      adj_ld_done <= 1'b1;
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    else
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      adj_ld_done <= 1'b0;
82 3 ash_riple
  end
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end
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85 19 edn_walter
reg  [39:0] time_adj_08n_32f;  // 39:32 ns, 31:0 ns_fraction
86 3 ash_riple
wire [15:0] time_adj_08n_08f;  // 15: 8 ns,  7:0 ns_fraction
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reg  [23:0] time_adj_00n_24f;  //           23:0 ns_fraction
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// delta-sigma circuit to keep the lower 24bit of time_adj
89 19 edn_walter
always @(posedge rst or posedge clk) begin
90 3 ash_riple
  if (rst) begin
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    time_adj_08n_32f <= 40'd0;
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    time_adj_00n_24f <= 24'd0;
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  end
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  else begin
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    time_adj_08n_32f <= time_adj[39: 0] + {16'd0, time_adj_00n_24f};  // add the delta
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    time_adj_00n_24f <= time_adj_08n_32f[23: 0];                      // save the delta
97 3 ash_riple
  end
98
end
99 19 edn_walter
assign time_adj_08n_08f = time_adj_08n_32f[39:24];  // output w/o the delta
100 3 ash_riple
 
101 41 edn_walter
reg  [37:0] time_acc_30n_08f_pre_pos;  // 37:8 ns , 7:0 ns_fraction
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reg  [37:0] time_acc_30n_08f_pre_neg;  // 37:8 ns , 7:0 ns_fraction
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wire        time_acc_48s_inc = (time_acc_30n_08f_pre_pos >= time_acc_modulo)? 1'b1: 1'b0;
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// time accumulator pre adder (48bit_s + 30bit_ns + 8bit_ns_fraction)
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always @(posedge rst or posedge clk) begin
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  if (rst) begin
107 45 edn_walter
    time_acc_30n_08f_pre_pos <= 38'd0;
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    time_acc_30n_08f_pre_neg <= 38'd0;
109 41 edn_walter
  end
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  else begin
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    if (time_ld) begin  // direct write
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      time_acc_30n_08f_pre_pos <= time_reg_ns_in + {22'd0, time_adj_08n_08f};
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      time_acc_30n_08f_pre_neg <= time_reg_ns_in + {22'd0, time_adj_08n_08f};
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    end
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    else begin
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      if (time_acc_48s_inc) begin
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        time_acc_30n_08f_pre_pos <= time_acc_30n_08f_pre_neg + {22'd0, time_adj_08n_08f};
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        time_acc_30n_08f_pre_neg <= time_acc_30n_08f_pre_neg + {22'd0, time_adj_08n_08f} - time_acc_modulo;
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      end
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      else begin
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        time_acc_30n_08f_pre_pos <= time_acc_30n_08f_pre_pos + {22'd0, time_adj_08n_08f};
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        time_acc_30n_08f_pre_neg <= time_acc_30n_08f_pre_pos + {22'd0, time_adj_08n_08f} - time_acc_modulo;
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      end
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    end
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  end
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end
127
 
128
reg  [37:0] time_acc_30n_08f;          // 37:8 ns , 7:0 ns_fraction
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reg  [47:0] time_acc_48s;              // 47:0 sec
130 3 ash_riple
// time accumulator (48bit_s + 30bit_ns + 8bit_ns_fraction)
131
always @(posedge rst or posedge clk) begin
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  if (rst) begin
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    time_acc_30n_08f <= 38'd0;
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    time_acc_48s     <= 48'd0;
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  end
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  else begin
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    if (time_ld) begin  // direct write
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      time_acc_30n_08f <= time_reg_ns_in;
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      time_acc_48s     <= time_reg_sec_in;
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    end
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    else begin
142 19 edn_walter
 
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      if (time_acc_48s_inc)
144 41 edn_walter
        time_acc_30n_08f <= time_acc_30n_08f_pre_neg;
145 19 edn_walter
      else
146 41 edn_walter
        time_acc_30n_08f <= time_acc_30n_08f_pre_pos;
147 19 edn_walter
 
148
      if (time_acc_48s_inc)
149
        time_acc_48s     <= time_acc_48s + 1;
150
      else
151
        time_acc_48s     <= time_acc_48s;
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153 3 ash_riple
    end
154
  end
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end
156
 
157
// time output (48bit_s + 30bit_ns + 8bit_ns_fraction)
158
assign time_reg_ns  = time_acc_30n_08f;
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assign time_reg_sec = time_acc_48s;
160 32 edn_walter
// time output (48bit_s + 32bit_ns)
161
assign time_ptp_ns  = {2'b00, time_acc_30n_08f[37:8]};
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assign time_ptp_sec = time_acc_48s;
163 3 ash_riple
 
164
endmodule

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