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[/] [ha1588/] [trunk/] [rtl/] [rtc/] [rtc.v] - Blame information for rev 19

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Line No. Rev Author Line
1 3 ash_riple
`timescale 1ns/1ns
2
 
3 15 edn_walter
module rtc (
4 3 ash_riple
  input rst, clk,
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  // 1. direct time adjustment: ToD set up
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  input time_ld,
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  input [37:0] time_reg_ns_in,   // 37:8 ns, 7:0 ns_fraction
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  input [47:0] time_reg_sec_in,  // 47:0 sec
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  // 2. frequency adjustment: frequency set up for drift compensation
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  input period_ld,
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  input [39:0] period_in,        // 39:32 ns, 31:0 ns_fraction
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  input [37:0] time_acc_modulo,  // 37: 8 ns,  7:0 ns_fraction
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  // 3. precise time adjustment: small time difference adjustment with a time mark
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  input adj_ld,
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  input [31:0] adj_ld_data,
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  input [39:0] period_adj,  // 39:32 ns, 31:0 ns_fraction
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  // time output          
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  output [37:0] time_reg_ns,  // 37:8 ns, 7:0 ns_fraction
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  output [47:0] time_reg_sec  // 47:0 sec 
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);
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reg  [39:0] period_fix;  // 39:32 ns, 31:0 ns_fraction
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reg  [31:0] adj_cnt;
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reg  [39:0] time_adj;    // 39:32 ns, 31:0 ns_fraction
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// frequency and small time difference adjustment registers
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always @(posedge rst or posedge clk) begin
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  if (rst) begin
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    period_fix <= 40'd0;
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    adj_cnt    <= 32'hffffffff;
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    time_adj   <= 40'd0;
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  end
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  else begin
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    if (period_ld)  // load period adjustment
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      period_fix <= period_in;
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    else
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      period_fix <= period_fix;
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    if (adj_ld)  // load precise time adjustment time mark
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      adj_cnt  <= adj_ld_data;
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    else if (adj_cnt==32'hffffffff)
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      adj_cnt  <= adj_cnt;  // no cycling
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    else
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      adj_cnt  <= adj_cnt - 1;  // counting down
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    if (adj_cnt==0)  // change period temparorily
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      time_adj <= period_fix + period_adj;
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    else
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      time_adj <= period_fix + 0;
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  end
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end
52
 
53 19 edn_walter
reg  [39:0] time_adj_08n_32f;  // 39:32 ns, 31:0 ns_fraction
54 3 ash_riple
wire [15:0] time_adj_08n_08f;  // 15: 8 ns,  7:0 ns_fraction
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reg  [23:0] time_adj_00n_24f;  //           23:0 ns_fraction
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// delta-sigma circuit to keep the lower 24bit of time_adj
57 19 edn_walter
always @(posedge rst or posedge clk) begin
58 3 ash_riple
  if (rst) begin
59 19 edn_walter
    time_adj_08n_32f <= 40'd0;
60 3 ash_riple
    time_adj_00n_24f <= 24'd0;
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  end
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  else begin
63 19 edn_walter
    time_adj_08n_32f <= time_adj[39: 0] + {16'd0, time_adj_00n_24f};  // add the delta
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    time_adj_00n_24f <= time_adj_08n_32f[23: 0];                      // save the delta
65 3 ash_riple
  end
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end
67 19 edn_walter
assign time_adj_08n_08f = time_adj_08n_32f[39:24];  // output w/o the delta
68 3 ash_riple
 
69
reg  [37:0] time_acc_30n_08f;  // 37:8 ns , 7:0 ns_fraction
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reg  [47:0] time_acc_48s;      // 47:0 sec
71 19 edn_walter
reg         time_acc_48s_inc;
72 3 ash_riple
// time accumulator (48bit_s + 30bit_ns + 8bit_ns_fraction)
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always @(posedge rst or posedge clk) begin
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  if (rst) begin
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    time_acc_30n_08f <= 38'd0;
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    time_acc_48s     <= 48'd0;
77 19 edn_walter
    time_acc_48s_inc <=  1'b0;
78 3 ash_riple
  end
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  else begin
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    if (time_ld) begin  // direct write
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      time_acc_30n_08f <= time_reg_ns_in;
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      time_acc_48s     <= time_reg_sec_in;
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    end
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    else begin
85 19 edn_walter
 
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      if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} >= time_acc_modulo)
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        time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f} - time_acc_modulo;
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      else
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        time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f};
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      if (time_acc_48s_inc)
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        time_acc_48s_inc <= 1'b0;
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      else if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} + {22'd0, time_adj_08n_08f} >= time_acc_modulo)
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        time_acc_48s_inc <= 1'b1;
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      else
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        time_acc_48s_inc <= 1'b0;
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      if (time_acc_48s_inc)
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        time_acc_48s     <= time_acc_48s + 1;
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      else
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        time_acc_48s     <= time_acc_48s;
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103 3 ash_riple
    end
104
  end
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end
106
 
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// time output (48bit_s + 30bit_ns + 8bit_ns_fraction)
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assign time_reg_ns  = time_acc_30n_08f;
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assign time_reg_sec = time_acc_48s;
110
 
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endmodule

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