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1 34 edn_walter
/*
2 38 edn_walter
 * reg.v
3 34 edn_walter
 *
4 37 edn_walter
 * Copyright (c) 2012, BABY&HW. All rights reserved.
5 34 edn_walter
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2.1 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, write to the Free Software
18
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19
 * MA 02110-1301  USA
20
 */
21
 
22 15 edn_walter
`timescale 1ns/1ns
23
 
24 17 edn_walter
module rgs (
25 16 edn_walter
  // generic bus interface
26
  input         rst,clk,
27
  input         wr_in,rd_in,
28 21 edn_walter
  input  [ 7:0] addr_in,
29 16 edn_walter
  input  [31:0] data_in,
30
  output [31:0] data_out,
31
  // rtc interface
32 17 edn_walter
  input         rtc_clk_in,
33
  output        rtc_rst_out,
34
  output        time_ld_out,
35 16 edn_walter
  output [37:0] time_reg_ns_out,
36
  output [47:0] time_reg_sec_out,
37 17 edn_walter
  output        period_ld_out,
38 16 edn_walter
  output [39:0] period_out,
39 17 edn_walter
  output        adj_ld_out,
40 16 edn_walter
  output [31:0] adj_ld_data_out,
41 17 edn_walter
  output [39:0] period_adj_out,
42 38 edn_walter
  input         adj_ld_done_in,
43 16 edn_walter
  input  [37:0] time_reg_ns_in,
44
  input  [47:0] time_reg_sec_in,
45 18 edn_walter
  // rx tsu interface
46 37 edn_walter
  output         rx_q_rst_out,
47
  output         rx_q_rd_clk_out,
48
  output         rx_q_rd_en_out,
49 43 edn_walter
  output [  7:0] rx_q_ptp_msgid_mask_out,
50 37 edn_walter
  input  [  7:0] rx_q_stat_in,
51
  input  [127:0] rx_q_data_in,
52 18 edn_walter
  // tx tsu interface
53 37 edn_walter
  output         tx_q_rst_out,
54
  output         tx_q_rd_clk_out,
55
  output         tx_q_rd_en_out,
56 43 edn_walter
  output [  7:0] tx_q_ptp_msgid_mask_out,
57 37 edn_walter
  input  [  7:0] tx_q_stat_in,
58
  input  [127:0] tx_q_data_in
59 15 edn_walter
);
60
 
61 17 edn_walter
parameter const_00 = 8'h00;
62
parameter const_04 = 8'h04;
63
parameter const_08 = 8'h08;
64 18 edn_walter
parameter const_0c = 8'h0C;
65 17 edn_walter
parameter const_10 = 8'h10;
66
parameter const_14 = 8'h14;
67
parameter const_18 = 8'h18;
68 18 edn_walter
parameter const_1c = 8'h1C;
69 17 edn_walter
parameter const_20 = 8'h20;
70
parameter const_24 = 8'h24;
71
parameter const_28 = 8'h28;
72 18 edn_walter
parameter const_2c = 8'h2C;
73 17 edn_walter
parameter const_30 = 8'h30;
74
parameter const_34 = 8'h34;
75
parameter const_38 = 8'h38;
76 18 edn_walter
parameter const_3c = 8'h3C;
77 17 edn_walter
parameter const_40 = 8'h40;
78
parameter const_44 = 8'h44;
79
parameter const_48 = 8'h48;
80 18 edn_walter
parameter const_4c = 8'h4C;
81
parameter const_50 = 8'h50;
82
parameter const_54 = 8'h54;
83
parameter const_58 = 8'h58;
84
parameter const_5c = 8'h5C;
85 33 edn_walter
parameter const_60 = 8'h60;
86
parameter const_64 = 8'h64;
87
parameter const_68 = 8'h68;
88
parameter const_6c = 8'h6C;
89 37 edn_walter
parameter const_70 = 8'h70;
90
parameter const_74 = 8'h74;
91
parameter const_78 = 8'h78;
92
parameter const_7c = 8'h7C;
93 17 edn_walter
 
94 21 edn_walter
wire cs_00 = (addr_in[7:2]==const_00[7:2])? 1'b1: 1'b0;
95
wire cs_04 = (addr_in[7:2]==const_04[7:2])? 1'b1: 1'b0;
96
wire cs_08 = (addr_in[7:2]==const_08[7:2])? 1'b1: 1'b0;
97
wire cs_0c = (addr_in[7:2]==const_0c[7:2])? 1'b1: 1'b0;
98
wire cs_10 = (addr_in[7:2]==const_10[7:2])? 1'b1: 1'b0;
99
wire cs_14 = (addr_in[7:2]==const_14[7:2])? 1'b1: 1'b0;
100
wire cs_18 = (addr_in[7:2]==const_18[7:2])? 1'b1: 1'b0;
101
wire cs_1c = (addr_in[7:2]==const_1c[7:2])? 1'b1: 1'b0;
102
wire cs_20 = (addr_in[7:2]==const_20[7:2])? 1'b1: 1'b0;
103
wire cs_24 = (addr_in[7:2]==const_24[7:2])? 1'b1: 1'b0;
104
wire cs_28 = (addr_in[7:2]==const_28[7:2])? 1'b1: 1'b0;
105
wire cs_2c = (addr_in[7:2]==const_2c[7:2])? 1'b1: 1'b0;
106
wire cs_30 = (addr_in[7:2]==const_30[7:2])? 1'b1: 1'b0;
107
wire cs_34 = (addr_in[7:2]==const_34[7:2])? 1'b1: 1'b0;
108
wire cs_38 = (addr_in[7:2]==const_38[7:2])? 1'b1: 1'b0;
109
wire cs_3c = (addr_in[7:2]==const_3c[7:2])? 1'b1: 1'b0;
110
wire cs_40 = (addr_in[7:2]==const_40[7:2])? 1'b1: 1'b0;
111
wire cs_44 = (addr_in[7:2]==const_44[7:2])? 1'b1: 1'b0;
112
wire cs_48 = (addr_in[7:2]==const_48[7:2])? 1'b1: 1'b0;
113
wire cs_4c = (addr_in[7:2]==const_4c[7:2])? 1'b1: 1'b0;
114
wire cs_50 = (addr_in[7:2]==const_50[7:2])? 1'b1: 1'b0;
115
wire cs_54 = (addr_in[7:2]==const_54[7:2])? 1'b1: 1'b0;
116
wire cs_58 = (addr_in[7:2]==const_58[7:2])? 1'b1: 1'b0;
117
wire cs_5c = (addr_in[7:2]==const_5c[7:2])? 1'b1: 1'b0;
118 33 edn_walter
wire cs_60 = (addr_in[7:2]==const_60[7:2])? 1'b1: 1'b0;
119
wire cs_64 = (addr_in[7:2]==const_64[7:2])? 1'b1: 1'b0;
120
wire cs_68 = (addr_in[7:2]==const_68[7:2])? 1'b1: 1'b0;
121
wire cs_6c = (addr_in[7:2]==const_6c[7:2])? 1'b1: 1'b0;
122 37 edn_walter
wire cs_70 = (addr_in[7:2]==const_70[7:2])? 1'b1: 1'b0;
123
wire cs_74 = (addr_in[7:2]==const_74[7:2])? 1'b1: 1'b0;
124
wire cs_78 = (addr_in[7:2]==const_78[7:2])? 1'b1: 1'b0;
125
wire cs_7c = (addr_in[7:2]==const_7c[7:2])? 1'b1: 1'b0;
126 17 edn_walter
 
127 33 edn_walter
reg [31:0] reg_00;  // ctrl 5 bit
128 38 edn_walter
reg [31:0] reg_04;  // null
129
reg [31:0] reg_08;  // null
130
reg [31:0] reg_0c;  // null
131 39 edn_walter
reg [31:0] reg_10;  // time 16 bit s
132
reg [31:0] reg_14;  // time 32 bit s
133
reg [31:0] reg_18;  // time 30 bit ns
134
reg [31:0] reg_1c;  // time  8 bit nsf
135
reg [31:0] reg_20;  // peri  8 bit ns
136
reg [31:0] reg_24;  // peri 32 bit nsf
137
reg [31:0] reg_28;  // ajpr  8 bit ns
138
reg [31:0] reg_2c;  // ajpr 32 bit nsf
139 17 edn_walter
reg [31:0] reg_30;  // ajld 32 bit
140 38 edn_walter
reg [31:0] reg_34;  // null
141
reg [31:0] reg_38;  // null
142
reg [31:0] reg_3c;  // null
143 39 edn_walter
reg [31:0] reg_40;  // ctrl  2 bit
144 38 edn_walter
reg [31:0] reg_44;  // qsta  8 bit
145 39 edn_walter
reg [31:0] reg_48;  // null
146 38 edn_walter
reg [31:0] reg_4c;  // null
147 39 edn_walter
reg [31:0] reg_50;  // rxqu 32 bit
148
reg [31:0] reg_54;  // rxqu 32 bit
149
reg [31:0] reg_58;  // rxqu 32 bit
150
reg [31:0] reg_5c;  // rxqu 32 bit
151
reg [31:0] reg_60;  // ctrl  2 bit
152
reg [31:0] reg_64;  // qsta  8 bit
153
reg [31:0] reg_68;  // null
154
reg [31:0] reg_6c;  // null
155 37 edn_walter
reg [31:0] reg_70;  // txqu 32 bit
156
reg [31:0] reg_74;  // txqu 32 bit
157
reg [31:0] reg_78;  // txqu 32 bit
158
reg [31:0] reg_7c;  // txqu 32 bit
159 17 edn_walter
 
160
// write registers
161
always @(posedge clk) begin
162
  if (wr_in && cs_00) reg_00 <= data_in;
163
  if (wr_in && cs_04) reg_04 <= data_in;
164
  if (wr_in && cs_08) reg_08 <= data_in;
165
  if (wr_in && cs_0c) reg_0c <= data_in;
166
  if (wr_in && cs_10) reg_10 <= data_in;
167
  if (wr_in && cs_14) reg_14 <= data_in;
168
  if (wr_in && cs_18) reg_18 <= data_in;
169
  if (wr_in && cs_1c) reg_1c <= data_in;
170
  if (wr_in && cs_20) reg_20 <= data_in;
171
  if (wr_in && cs_24) reg_24 <= data_in;
172
  if (wr_in && cs_28) reg_28 <= data_in;
173
  if (wr_in && cs_2c) reg_2c <= data_in;
174
  if (wr_in && cs_30) reg_30 <= data_in;
175
  if (wr_in && cs_34) reg_34 <= data_in;
176
  if (wr_in && cs_38) reg_38 <= data_in;
177
  if (wr_in && cs_3c) reg_3c <= data_in;
178
  if (wr_in && cs_40) reg_40 <= data_in;
179
  if (wr_in && cs_44) reg_44 <= data_in;
180
  if (wr_in && cs_48) reg_48 <= data_in;
181
  if (wr_in && cs_4c) reg_4c <= data_in;
182 18 edn_walter
  if (wr_in && cs_50) reg_50 <= data_in;
183
  if (wr_in && cs_54) reg_54 <= data_in;
184
  if (wr_in && cs_58) reg_58 <= data_in;
185
  if (wr_in && cs_5c) reg_5c <= data_in;
186 33 edn_walter
  if (wr_in && cs_60) reg_60 <= data_in;
187
  if (wr_in && cs_64) reg_64 <= data_in;
188
  if (wr_in && cs_68) reg_68 <= data_in;
189
  if (wr_in && cs_6c) reg_6c <= data_in;
190 37 edn_walter
  if (wr_in && cs_70) reg_70 <= data_in;
191
  if (wr_in && cs_74) reg_74 <= data_in;
192
  if (wr_in && cs_78) reg_78 <= data_in;
193
  if (wr_in && cs_7c) reg_7c <= data_in;
194 17 edn_walter
end
195
 
196
// read registers
197
reg  [37:0] time_reg_ns_int;
198
reg  [47:0] time_reg_sec_int;
199 37 edn_walter
reg  [127:0] rx_q_data_int;
200
reg  [  7:0] rx_q_stat_int;
201
reg  [127:0] tx_q_data_int;
202
reg  [  7:0] tx_q_stat_int;
203 23 edn_walter
reg         time_ok;
204 31 edn_walter
reg         rxqu_ok;
205
reg         txqu_ok;
206 17 edn_walter
 
207
reg  [31:0] data_out_reg;
208
always @(posedge clk) begin
209 37 edn_walter
  // register mapping: RTC
210 45 edn_walter
  if (rd_in && cs_00) data_out_reg <= {27'd0, reg_00[ 4: 2], adj_ld_done_in, time_ok};
211
  if (rd_in && cs_04) data_out_reg <= 32'd0;
212
  if (rd_in && cs_08) data_out_reg <= 32'd0;
213
  if (rd_in && cs_0c) data_out_reg <= 32'd0;
214 38 edn_walter
  if (rd_in && cs_10) data_out_reg <= {16'd0, time_reg_sec_int[47:32]};
215
  if (rd_in && cs_14) data_out_reg <=         time_reg_sec_int[31: 0] ;
216
  if (rd_in && cs_18) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]};
217
  if (rd_in && cs_1c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]};
218 45 edn_walter
  if (rd_in && cs_20) data_out_reg <= {24'd0, reg_20[ 7: 0]};
219 18 edn_walter
  if (rd_in && cs_24) data_out_reg <= reg_24;
220 45 edn_walter
  if (rd_in && cs_28) data_out_reg <= {24'd0, reg_28[ 7: 0]};
221 18 edn_walter
  if (rd_in && cs_2c) data_out_reg <= reg_2c;
222
  if (rd_in && cs_30) data_out_reg <= reg_30;
223 45 edn_walter
  if (rd_in && cs_34) data_out_reg <= 32'd0;
224
  if (rd_in && cs_38) data_out_reg <= 32'd0;
225
  if (rd_in && cs_3c) data_out_reg <= 32'd0;
226 39 edn_walter
  // register mapping: TSU RX
227 45 edn_walter
  if (rd_in && cs_40) data_out_reg <= {30'd0, reg_40[ 1], rxqu_ok};
228
  if (rd_in && cs_44) data_out_reg <= {reg_44[31:24], 16'd0, rx_q_stat_int[ 7: 0]};
229
  if (rd_in && cs_48) data_out_reg <= 32'd0;
230
  if (rd_in && cs_4c) data_out_reg <= 32'd0;
231 39 edn_walter
  if (rd_in && cs_50) data_out_reg <= rx_q_data_int[127: 96];
232
  if (rd_in && cs_54) data_out_reg <= rx_q_data_int[ 95: 64];
233
  if (rd_in && cs_58) data_out_reg <= rx_q_data_int[ 63: 32];
234
  if (rd_in && cs_5c) data_out_reg <= rx_q_data_int[ 31:  0];
235
  // register mapping: TSU TX
236 45 edn_walter
  if (rd_in && cs_60) data_out_reg <= {30'd0, reg_60[ 1], txqu_ok};
237
  if (rd_in && cs_64) data_out_reg <= {reg_64[31:24], 16'd0, tx_q_stat_int[ 7: 0]};
238
  if (rd_in && cs_68) data_out_reg <= 32'd0;
239
  if (rd_in && cs_6c) data_out_reg <= 32'd0;
240 37 edn_walter
  if (rd_in && cs_70) data_out_reg <= tx_q_data_int[127: 96];
241
  if (rd_in && cs_74) data_out_reg <= tx_q_data_int[ 95: 64];
242
  if (rd_in && cs_78) data_out_reg <= tx_q_data_int[ 63: 32];
243
  if (rd_in && cs_7c) data_out_reg <= tx_q_data_int[ 31:  0];
244 17 edn_walter
end
245
assign data_out = data_out_reg;
246
 
247 33 edn_walter
// register mapping: RTC
248 18 edn_walter
//wire       = reg_00[ 7];
249
//wire       = reg_00[ 6];
250
//wire       = reg_00[ 5];
251
wire rtc_rst = reg_00[ 4];
252
wire time_ld = reg_00[ 3];
253
wire perd_ld = reg_00[ 2];
254
wire adjt_ld = reg_00[ 1];
255
wire time_rd = reg_00[ 0];
256 43 edn_walter
assign time_reg_sec_out [47:0] = {reg_10[15: 0], reg_14[31: 0]};
257
assign time_reg_ns_out  [37:0] = {reg_18[29: 0], reg_1c[ 7: 0]};
258
assign period_out       [39:0] = {reg_20[ 7: 0], reg_24[31: 0]};
259
assign period_adj_out   [39:0] = {reg_28[ 7: 0], reg_2c[31: 0]};
260
assign adj_ld_data_out  [31:0] =  reg_30[31: 0];
261 37 edn_walter
 
262 39 edn_walter
// register mapping: TSU RX
263 38 edn_walter
//wire       = reg_40[ 7];
264
//wire       = reg_40[ 6];
265
//wire       = reg_40[ 5];
266
//wire       = reg_40[ 4];
267 39 edn_walter
//wire       = reg_40[ 3];
268
//wire       = reg_40[ 2];
269
wire rxq_rst = reg_40[ 1];
270
wire rxqu_rd = reg_40[ 0];
271 43 edn_walter
assign rx_q_ptp_msgid_mask_out [7:0] = reg_44[31:24];
272 39 edn_walter
 
273
// register mapping: TSU TX
274
//wire       = reg_60[ 7];
275
//wire       = reg_60[ 6];
276
//wire       = reg_60[ 5];
277
//wire       = reg_60[ 4];
278
//wire       = reg_60[ 3];
279
//wire       = reg_60[ 2];
280
wire txq_rst = reg_60[ 1];
281
wire txqu_rd = reg_60[ 0];
282 43 edn_walter
assign tx_q_ptp_msgid_mask_out [7:0] = reg_64[31:24];
283 37 edn_walter
// TODO: add configurable VLANTPID values
284 17 edn_walter
 
285
// real time clock
286 23 edn_walter
reg rtc_rst_s1, rtc_rst_s2, rtc_rst_s3;
287
assign rtc_rst_out = rtc_rst_s2 && !rtc_rst_s3;
288
always @(posedge rtc_clk_in) begin
289
  rtc_rst_s1 <= rtc_rst;
290
  rtc_rst_s2 <= rtc_rst_s1;
291
  rtc_rst_s3 <= rtc_rst_s2;
292 17 edn_walter
end
293
 
294 23 edn_walter
reg time_ld_s1, time_ld_s2, time_ld_s3;
295
assign time_ld_out = time_ld_s2 && !time_ld_s3;
296
always @(posedge rtc_clk_in) begin
297
  time_ld_s1 <= time_ld;
298
  time_ld_s2 <= time_ld_s1;
299
  time_ld_s3 <= time_ld_s2;
300 17 edn_walter
end
301
 
302 23 edn_walter
reg perd_ld_s1, perd_ld_s2, perd_ld_s3;
303
assign period_ld_out  = perd_ld_s2 && !perd_ld_s3;
304
always @(posedge rtc_clk_in) begin
305
  perd_ld_s1 <= perd_ld;
306
  perd_ld_s2 <= perd_ld_s1;
307
  perd_ld_s3 <= perd_ld_s2;
308 17 edn_walter
end
309
 
310 23 edn_walter
reg adjt_ld_s1, adjt_ld_s2, adjt_ld_s3;
311
assign adj_ld_out = adjt_ld_s2 && !adjt_ld_s3;
312
always @(posedge rtc_clk_in) begin
313
  adjt_ld_s1 <= adjt_ld;
314
  adjt_ld_s2 <= adjt_ld_s1;
315
  adjt_ld_s3 <= adjt_ld_s2;
316 17 edn_walter
end
317
 
318 23 edn_walter
// RTC time read CDC hand-shaking
319
reg time_rd_s1, time_rd_s2, time_rd_s3;
320
wire time_rd_ack = time_rd_s2 && !time_rd_s3;
321 17 edn_walter
always @(posedge rtc_clk_in) begin
322 23 edn_walter
  time_rd_s1 <= time_rd;
323
  time_rd_s2 <= time_rd_s1;
324
  time_rd_s3 <= time_rd_s2;
325 17 edn_walter
end
326
 
327
always @(posedge rtc_clk_in) begin
328 23 edn_walter
  if (time_rd_ack) begin
329 17 edn_walter
    time_reg_ns_int  <= time_reg_ns_in;
330
    time_reg_sec_int <= time_reg_sec_in;
331
  end
332
end
333
 
334 23 edn_walter
reg time_rd_d1;
335
wire time_rd_req = time_rd && !time_rd_d1;
336
always @(posedge clk) begin
337
  time_rd_d1 <= time_rd;
338
end
339
 
340
always @(posedge clk or posedge time_rd_ack) begin
341
  if (time_rd_ack)
342
    time_ok <= 1'b1;
343
  else if (time_rd_req)
344
    time_ok <= 1'b0;
345
end
346
 
347 18 edn_walter
// rx time stamp queue
348
assign rx_q_rd_clk_out = clk;
349 17 edn_walter
 
350 18 edn_walter
reg rxq_rst_d1, rxq_rst_d2, rxq_rst_d3;
351
assign rx_q_rst_out = rxq_rst_d2 && !rxq_rst_d3;
352 17 edn_walter
always @(posedge clk) begin
353 18 edn_walter
  rxq_rst_d1 <= rxq_rst;
354
  rxq_rst_d2 <= rxq_rst_d1;
355
  rxq_rst_d3 <= rxq_rst_d2;
356 17 edn_walter
end
357
 
358 31 edn_walter
reg rxqu_rd_d1, rxqu_rd_d2, rxqu_rd_d3, rxqu_rd_d4, rxqu_rd_d5;
359 18 edn_walter
assign rx_q_rd_en_out = rxqu_rd_d2 && !rxqu_rd_d3;
360 31 edn_walter
wire   rx_q_rd_req    = rxqu_rd_d2 && !rxqu_rd_d3;
361
wire   rx_q_rd_ack    = rxqu_rd_d4 && !rxqu_rd_d5;
362 17 edn_walter
always @(posedge clk) begin
363 18 edn_walter
  rxqu_rd_d1 <= rxqu_rd;
364
  rxqu_rd_d2 <= rxqu_rd_d1;
365
  rxqu_rd_d3 <= rxqu_rd_d2;
366 31 edn_walter
  rxqu_rd_d4 <= rxqu_rd_d3;
367
  rxqu_rd_d5 <= rxqu_rd_d4;
368 17 edn_walter
end
369
 
370
always @(posedge clk) begin
371 31 edn_walter
  if (rx_q_rd_ack)
372
    rxqu_ok <= 1'b1;
373
  else if (rx_q_rd_req)
374
    rxqu_ok <= 1'b0;
375
end
376
 
377
always @(posedge clk) begin
378 18 edn_walter
  rx_q_data_int <= rx_q_data_in;
379
  rx_q_stat_int <= rx_q_stat_in;
380 17 edn_walter
end
381
 
382 18 edn_walter
// tx time stamp queue
383
assign tx_q_rd_clk_out = clk;
384
 
385
reg txq_rst_d1, txq_rst_d2, txq_rst_d3;
386
assign tx_q_rst_out = txq_rst_d2 && !txq_rst_d3;
387
always @(posedge clk) begin
388
  txq_rst_d1 <= txq_rst;
389
  txq_rst_d2 <= txq_rst_d1;
390
  txq_rst_d3 <= txq_rst_d2;
391
end
392
 
393 31 edn_walter
reg txqu_rd_d1, txqu_rd_d2, txqu_rd_d3, txqu_rd_d4, txqu_rd_d5;
394 18 edn_walter
assign tx_q_rd_en_out = txqu_rd_d2 && !txqu_rd_d3;
395 31 edn_walter
wire   tx_q_rd_req    = txqu_rd_d2 && !txqu_rd_d3;
396
wire   tx_q_rd_ack    = txqu_rd_d4 && !txqu_rd_d5;
397 18 edn_walter
always @(posedge clk) begin
398
  txqu_rd_d1 <= txqu_rd;
399
  txqu_rd_d2 <= txqu_rd_d1;
400
  txqu_rd_d3 <= txqu_rd_d2;
401 31 edn_walter
  txqu_rd_d4 <= txqu_rd_d3;
402
  txqu_rd_d5 <= txqu_rd_d4;
403 18 edn_walter
end
404
 
405
always @(posedge clk) begin
406 31 edn_walter
  if (tx_q_rd_ack)
407
    txqu_ok <= 1'b1;
408
  else if (tx_q_rd_req)
409
    txqu_ok <= 1'b0;
410
end
411
 
412
always @(posedge clk) begin
413 18 edn_walter
  tx_q_data_int <= tx_q_data_in;
414
  tx_q_stat_int <= tx_q_stat_in;
415
end
416
 
417 15 edn_walter
endmodule

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