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[/] [ha1588/] [trunk/] [rtl/] [reg/] [reg.v] - Blame information for rev 18

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Line No. Rev Author Line
1 15 edn_walter
`timescale 1ns/1ns
2
 
3 17 edn_walter
module rgs (
4 16 edn_walter
  // generic bus interface
5
  input         rst,clk,
6
  input         wr_in,rd_in,
7 17 edn_walter
  input  [ 5:0] addr_in,
8 16 edn_walter
  input  [31:0] data_in,
9
  output [31:0] data_out,
10
  // rtc interface
11 17 edn_walter
  input         rtc_clk_in,
12
  output        rtc_rst_out,
13
  output        time_ld_out,
14 16 edn_walter
  output [37:0] time_reg_ns_out,
15
  output [47:0] time_reg_sec_out,
16 17 edn_walter
  output        period_ld_out,
17 16 edn_walter
  output [39:0] period_out,
18
  output [37:0] time_acc_modulo_out,
19 17 edn_walter
  output        adj_ld_out,
20 16 edn_walter
  output [31:0] adj_ld_data_out,
21 17 edn_walter
  output [39:0] period_adj_out,
22 16 edn_walter
  input  [37:0] time_reg_ns_in,
23
  input  [47:0] time_reg_sec_in,
24 18 edn_walter
  // rx tsu interface
25
  output        rx_q_rst_out,
26
  output        rx_q_rd_clk_out,
27
  output        rx_q_rd_en_out,
28
  input  [ 7:0] rx_q_stat_in,
29
  input  [55:0] rx_q_data_in,
30
  // tx tsu interface
31
  output        tx_q_rst_out,
32
  output        tx_q_rd_clk_out,
33
  output        tx_q_rd_en_out,
34
  input  [ 7:0] tx_q_stat_in,
35
  input  [55:0] tx_q_data_in
36 15 edn_walter
);
37
 
38 17 edn_walter
parameter const_00 = 8'h00;
39
parameter const_04 = 8'h04;
40
parameter const_08 = 8'h08;
41 18 edn_walter
parameter const_0c = 8'h0C;
42 17 edn_walter
parameter const_10 = 8'h10;
43
parameter const_14 = 8'h14;
44
parameter const_18 = 8'h18;
45 18 edn_walter
parameter const_1c = 8'h1C;
46 17 edn_walter
parameter const_20 = 8'h20;
47
parameter const_24 = 8'h24;
48
parameter const_28 = 8'h28;
49 18 edn_walter
parameter const_2c = 8'h2C;
50 17 edn_walter
parameter const_30 = 8'h30;
51
parameter const_34 = 8'h34;
52
parameter const_38 = 8'h38;
53 18 edn_walter
parameter const_3c = 8'h3C;
54 17 edn_walter
parameter const_40 = 8'h40;
55
parameter const_44 = 8'h44;
56
parameter const_48 = 8'h48;
57 18 edn_walter
parameter const_4c = 8'h4C;
58
parameter const_50 = 8'h50;
59
parameter const_54 = 8'h54;
60
parameter const_58 = 8'h58;
61
parameter const_5c = 8'h5C;
62 17 edn_walter
 
63
wire cs_00 = (addr_in[5:0]==const_00[5:0])? 1'b1: 1'b0;
64
wire cs_04 = (addr_in[5:0]==const_04[5:0])? 1'b1: 1'b0;
65
wire cs_08 = (addr_in[5:0]==const_08[5:0])? 1'b1: 1'b0;
66
wire cs_0c = (addr_in[5:0]==const_0c[5:0])? 1'b1: 1'b0;
67
wire cs_10 = (addr_in[5:0]==const_10[5:0])? 1'b1: 1'b0;
68
wire cs_14 = (addr_in[5:0]==const_14[5:0])? 1'b1: 1'b0;
69
wire cs_18 = (addr_in[5:0]==const_18[5:0])? 1'b1: 1'b0;
70
wire cs_1c = (addr_in[5:0]==const_1c[5:0])? 1'b1: 1'b0;
71
wire cs_20 = (addr_in[5:0]==const_20[5:0])? 1'b1: 1'b0;
72
wire cs_24 = (addr_in[5:0]==const_24[5:0])? 1'b1: 1'b0;
73
wire cs_28 = (addr_in[5:0]==const_28[5:0])? 1'b1: 1'b0;
74
wire cs_2c = (addr_in[5:0]==const_2c[5:0])? 1'b1: 1'b0;
75
wire cs_30 = (addr_in[5:0]==const_30[5:0])? 1'b1: 1'b0;
76
wire cs_34 = (addr_in[5:0]==const_34[5:0])? 1'b1: 1'b0;
77
wire cs_38 = (addr_in[5:0]==const_38[5:0])? 1'b1: 1'b0;
78
wire cs_3c = (addr_in[5:0]==const_3c[5:0])? 1'b1: 1'b0;
79
wire cs_40 = (addr_in[5:0]==const_40[5:0])? 1'b1: 1'b0;
80
wire cs_44 = (addr_in[5:0]==const_44[5:0])? 1'b1: 1'b0;
81
wire cs_48 = (addr_in[5:0]==const_48[5:0])? 1'b1: 1'b0;
82
wire cs_4c = (addr_in[5:0]==const_4c[5:0])? 1'b1: 1'b0;
83 18 edn_walter
wire cs_50 = (addr_in[5:0]==const_50[5:0])? 1'b1: 1'b0;
84
wire cs_54 = (addr_in[5:0]==const_54[5:0])? 1'b1: 1'b0;
85
wire cs_58 = (addr_in[5:0]==const_58[5:0])? 1'b1: 1'b0;
86
wire cs_5c = (addr_in[5:0]==const_5c[5:0])? 1'b1: 1'b0;
87 17 edn_walter
 
88 18 edn_walter
reg [31:0] reg_00;  // ctrl 12 bit
89
reg [31:0] reg_04;  // qsta 16 bit
90
reg [31:0] reg_08;  // 
91
reg [31:0] reg_0c;  // 
92 17 edn_walter
reg [31:0] reg_10;  // tout 16 s
93
reg [31:0] reg_14;  // tout 32 s
94
reg [31:0] reg_18;  // tout 30 ns
95
reg [31:0] reg_1c;  // tout  8 nsf
96
reg [31:0] reg_20;  // peri  8 ns
97
reg [31:0] reg_24;  // peri 32 nsf
98
reg [31:0] reg_28;  // amod 30 ns
99
reg [31:0] reg_2c;  // amod  8 nsf
100
reg [31:0] reg_30;  // ajld 32 bit
101
reg [31:0] reg_34;  // 
102
reg [31:0] reg_38;  // ajpr  8 ns
103
reg [31:0] reg_3c;  // ajpr 32 nsf
104
reg [31:0] reg_40;  // tmin 16 s
105
reg [31:0] reg_44;  // tmin 32 s
106
reg [31:0] reg_48;  // tmin 30 ns
107
reg [31:0] reg_4c;  // tmin  8 nsf
108 18 edn_walter
reg [31:0] reg_50;  // rxqu 24 bit
109
reg [31:0] reg_54;  // rxqu 32 bit
110
reg [31:0] reg_58;  // txqu 24 bit
111
reg [31:0] reg_5c;  // txqu 32 bit
112 17 edn_walter
 
113
// write registers
114
always @(posedge clk) begin
115
  if (wr_in && cs_00) reg_00 <= data_in;
116
  if (wr_in && cs_04) reg_04 <= data_in;
117
  if (wr_in && cs_08) reg_08 <= data_in;
118
  if (wr_in && cs_0c) reg_0c <= data_in;
119
  if (wr_in && cs_10) reg_10 <= data_in;
120
  if (wr_in && cs_14) reg_14 <= data_in;
121
  if (wr_in && cs_18) reg_18 <= data_in;
122
  if (wr_in && cs_1c) reg_1c <= data_in;
123
  if (wr_in && cs_20) reg_20 <= data_in;
124
  if (wr_in && cs_24) reg_24 <= data_in;
125
  if (wr_in && cs_28) reg_28 <= data_in;
126
  if (wr_in && cs_2c) reg_2c <= data_in;
127
  if (wr_in && cs_30) reg_30 <= data_in;
128
  if (wr_in && cs_34) reg_34 <= data_in;
129
  if (wr_in && cs_38) reg_38 <= data_in;
130
  if (wr_in && cs_3c) reg_3c <= data_in;
131
  if (wr_in && cs_40) reg_40 <= data_in;
132
  if (wr_in && cs_44) reg_44 <= data_in;
133
  if (wr_in && cs_48) reg_48 <= data_in;
134
  if (wr_in && cs_4c) reg_4c <= data_in;
135 18 edn_walter
  if (wr_in && cs_50) reg_50 <= data_in;
136
  if (wr_in && cs_54) reg_54 <= data_in;
137
  if (wr_in && cs_58) reg_58 <= data_in;
138
  if (wr_in && cs_5c) reg_5c <= data_in;
139 17 edn_walter
end
140
 
141
// read registers
142
reg  [37:0] time_reg_ns_int;
143
reg  [47:0] time_reg_sec_int;
144 18 edn_walter
reg  [55:0] rx_q_data_int;
145
reg  [ 7:0] rx_q_stat_int;
146
reg  [55:0] tx_q_data_int;
147
reg  [ 7:0] tx_q_stat_int;
148 17 edn_walter
 
149
reg  [31:0] data_out_reg;
150
always @(posedge clk) begin
151 18 edn_walter
  if (rd_in && cs_00) data_out_reg <= reg_00;
152
  if (rd_in && cs_04) data_out_reg <= {8'd0, rx_q_stat_int[ 7: 0], 8'd0, tx_q_stat_int[ 7: 0]};
153
  if (rd_in && cs_08) data_out_reg <= reg_08;
154
  if (rd_in && cs_0c) data_out_reg <= reg_0c;
155
  if (rd_in && cs_10) data_out_reg <= reg_10;
156
  if (rd_in && cs_14) data_out_reg <= reg_14;
157
  if (rd_in && cs_18) data_out_reg <= reg_18;
158
  if (rd_in && cs_1c) data_out_reg <= reg_1c;
159
  if (rd_in && cs_20) data_out_reg <= reg_20;
160
  if (rd_in && cs_24) data_out_reg <= reg_24;
161
  if (rd_in && cs_28) data_out_reg <= reg_28;
162
  if (rd_in && cs_2c) data_out_reg <= reg_2c;
163
  if (rd_in && cs_30) data_out_reg <= reg_30;
164
  if (rd_in && cs_34) data_out_reg <= reg_34;
165
  if (rd_in && cs_38) data_out_reg <= reg_38;
166
  if (rd_in && cs_3c) data_out_reg <= reg_3c;
167
  if (rd_in && cs_40) data_out_reg <= {16'd0, time_reg_sec_int[47:32]};
168
  if (rd_in && cs_44) data_out_reg <=         time_reg_sec_int[31: 0];
169
  if (rd_in && cs_48) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]};
170
  if (rd_in && cs_4c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]};
171
  if (rd_in && cs_50) data_out_reg <= { 8'd0, rx_q_data_int[55:32]};
172
  if (rd_in && cs_54) data_out_reg <=         rx_q_data_int[31: 0];
173
  if (rd_in && cs_58) data_out_reg <= { 8'd0, tx_q_data_int[55:32]};
174
  if (rd_in && cs_5c) data_out_reg <=         tx_q_data_int[31: 0];
175 17 edn_walter
end
176
assign data_out = data_out_reg;
177
 
178
// register mapping
179 18 edn_walter
wire rxq_rst = reg_00[11];
180
wire rxqu_rd = reg_00[10];
181
wire txq_rst = reg_00[ 9];
182
wire txqu_rd = reg_00[ 8];
183
//wire       = reg_00[ 7];
184
//wire       = reg_00[ 6];
185
//wire       = reg_00[ 5];
186
wire rtc_rst = reg_00[ 4];
187
wire time_ld = reg_00[ 3];
188
wire perd_ld = reg_00[ 2];
189
wire adjt_ld = reg_00[ 1];
190
wire time_rd = reg_00[ 0];
191 17 edn_walter
assign time_reg_sec_out   [47:0] = {reg_10[15: 0], reg_14[31: 0]};
192
assign time_reg_ns_out    [37:0] = {reg_18[29: 0], reg_1c[ 7: 0]};
193
assign period_out         [39:0] = {reg_20[ 7: 0], reg_24[31: 0]};
194
assign time_acc_modulo_out[37:0] = {reg_28[29: 0], reg_2c[ 7: 0]};
195
assign adj_ld_data_out    [31:0] =  reg_30[31: 0];
196
assign period_adj_out     [39:0] = {reg_38[ 7: 0], reg_3c[31: 0]};
197
 
198
// real time clock
199
reg rtc_rst_d1, rtc_rst_d2, rtc_rst_d3;
200
assign rtc_rst_out = rtc_rst_d2 && !rtc_rst_d3;
201
always @(posedge clk) begin
202
  rtc_rst_d1 <= rtc_rst;
203
  rtc_rst_d2 <= rtc_rst_d1;
204
  rtc_rst_d3 <= rtc_rst_d2;
205
end
206
 
207
reg time_ld_d1, time_ld_d2, time_ld_d3;
208
assign time_ld_out = time_ld_d2 && !time_ld_d3;
209
always @(posedge clk) begin
210
  time_ld_d1 <= time_ld;
211
  time_ld_d2 <= time_ld_d1;
212
  time_ld_d3 <= time_ld_d2;
213
end
214
 
215
reg perd_ld_d1, perd_ld_d2, perd_ld_d3;
216
assign period_ld_out  = perd_ld_d2 && !perd_ld_d3;
217
always @(posedge clk) begin
218
  perd_ld_d1 <= perd_ld;
219
  perd_ld_d2 <= perd_ld_d1;
220
  perd_ld_d3 <= perd_ld_d2;
221
end
222
 
223
reg adjt_ld_d1, adjt_ld_d2, adjt_ld_d3;
224
assign adj_ld_out = adjt_ld_d2 && !adjt_ld_d3;
225
always @(posedge clk) begin
226
  adjt_ld_d1 <= adjt_ld;
227
  adjt_ld_d2 <= adjt_ld_d1;
228
  adjt_ld_d3 <= adjt_ld_d2;
229
end
230
 
231
reg time_rd_d1, time_rd_d2, time_rd_d3;
232
wire time_reg_in_latch = time_rd_d2 && !time_rd_d3;
233
always @(posedge rtc_clk_in) begin
234
  time_rd_d1 <= time_rd;
235
  time_rd_d2 <= time_rd_d1;
236
  time_rd_d3 <= time_rd_d2;
237
end
238
 
239
always @(posedge rtc_clk_in) begin
240
  if (time_reg_in_latch) begin
241
    time_reg_ns_int  <= time_reg_ns_in;
242
    time_reg_sec_int <= time_reg_sec_in;
243
  end
244
end
245
 
246 18 edn_walter
// rx time stamp queue
247
assign rx_q_rd_clk_out = clk;
248 17 edn_walter
 
249 18 edn_walter
reg rxq_rst_d1, rxq_rst_d2, rxq_rst_d3;
250
assign rx_q_rst_out = rxq_rst_d2 && !rxq_rst_d3;
251 17 edn_walter
always @(posedge clk) begin
252 18 edn_walter
  rxq_rst_d1 <= rxq_rst;
253
  rxq_rst_d2 <= rxq_rst_d1;
254
  rxq_rst_d3 <= rxq_rst_d2;
255 17 edn_walter
end
256
 
257 18 edn_walter
reg rxqu_rd_d1, rxqu_rd_d2, rxqu_rd_d3;
258
assign rx_q_rd_en_out = rxqu_rd_d2 && !rxqu_rd_d3;
259 17 edn_walter
always @(posedge clk) begin
260 18 edn_walter
  rxqu_rd_d1 <= rxqu_rd;
261
  rxqu_rd_d2 <= rxqu_rd_d1;
262
  rxqu_rd_d3 <= rxqu_rd_d2;
263 17 edn_walter
end
264
 
265
always @(posedge clk) begin
266 18 edn_walter
  rx_q_data_int <= rx_q_data_in;
267
  rx_q_stat_int <= rx_q_stat_in;
268 17 edn_walter
end
269
 
270 18 edn_walter
// tx time stamp queue
271
assign tx_q_rd_clk_out = clk;
272
 
273
reg txq_rst_d1, txq_rst_d2, txq_rst_d3;
274
assign tx_q_rst_out = txq_rst_d2 && !txq_rst_d3;
275
always @(posedge clk) begin
276
  txq_rst_d1 <= txq_rst;
277
  txq_rst_d2 <= txq_rst_d1;
278
  txq_rst_d3 <= txq_rst_d2;
279
end
280
 
281
reg txqu_rd_d1, txqu_rd_d2, txqu_rd_d3;
282
assign tx_q_rd_en_out = txqu_rd_d2 && !txqu_rd_d3;
283
always @(posedge clk) begin
284
  txqu_rd_d1 <= txqu_rd;
285
  txqu_rd_d2 <= txqu_rd_d1;
286
  txqu_rd_d3 <= txqu_rd_d2;
287
end
288
 
289
always @(posedge clk) begin
290
  tx_q_data_int <= tx_q_data_in;
291
  tx_q_stat_int <= tx_q_stat_in;
292
end
293
 
294 15 edn_walter
endmodule

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