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1 18 edn_walter
## Generated SDC file "ha1588.sdc"
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## Copyright (C) 1991-2011 Altera Corporation
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, Altera MegaCore Function License
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## Agreement, or other applicable license agreement, including,
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## without limitation, that your use is for the sole purpose of
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## programming logic devices manufactured by Altera and sold by
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## Altera or its authorized distributors.  Please refer to the
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## applicable agreement for further details.
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## VENDOR  "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version"
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## DATE    "Sat Mar 31 15:03:15 2012"
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##
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## DEVICE  "EP3C5F256C6"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}]
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create_clock -name {rtc_clk} -period 8.000 -waveform { 0.000 4.000 } [get_ports {rtc_clk}]
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create_clock -name {tx_gmii_clk} -period 8.000 -waveform { 0.000 4.000 } [get_ports {tx_gmii_clk}]
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create_clock -name {rx_gmii_clk} -period 8.000 -waveform { 0.000 4.000 } [get_ports {rx_gmii_clk}]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}]  0.020
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set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}]  0.020
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set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {rtc_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {rtc_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {rx_gmii_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {rx_gmii_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {tx_gmii_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {tx_gmii_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}]  0.020
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set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}]  0.020
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set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {rtc_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {rtc_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {rx_gmii_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {rx_gmii_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {tx_gmii_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {tx_gmii_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  0.020
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set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  0.020
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set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rx_gmii_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rx_gmii_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {tx_gmii_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {tx_gmii_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  0.020
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set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  0.020
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set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rx_gmii_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rx_gmii_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {tx_gmii_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {tx_gmii_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {rtc_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {rtc_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {rx_gmii_clk}]  0.020
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set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {rx_gmii_clk}]  0.020
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set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {rtc_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {rtc_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {rx_gmii_clk}]  0.020
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set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {rx_gmii_clk}]  0.020
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set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {rtc_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {rtc_clk}]  0.040
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set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {tx_gmii_clk}]  0.020
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set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {tx_gmii_clk}]  0.020
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set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {rtc_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {rtc_clk}]  0.040
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set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {tx_gmii_clk}]  0.020
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set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {tx_gmii_clk}]  0.020
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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set_clock_groups -exclusive -group [get_clocks {clk}] \
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                            -group [get_clocks {rtc_clk}] \
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                            -group [get_clocks {rx_gmii_clk}] \
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                            -group [get_clocks {tx_gmii_clk}]
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#**************************************************************
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# Set False Path
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#**************************************************************
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set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_gd9:dffpipe18|dffe19a*}]
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set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_fd9:dffpipe15|dffe16a*}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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