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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 356

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 38 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.57  2005/02/21 11:35:33  igorm
45
// Defer indication fixed.
46
//
47 329 igorm
// Revision 1.56  2004/04/30 10:30:00  igorm
48
// Accidently deleted line put back.
49
//
50 323 igorm
// Revision 1.55  2004/04/26 15:26:23  igorm
51
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
52
//   previous update of the core.
53
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
54
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
55
//   register. (thanks to Mathias and Torbjorn)
56
// - Multicast reception was fixed. Thanks to Ulrich Gries
57
//
58 321 igorm
// Revision 1.54  2003/11/12 18:24:59  tadejm
59
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
60
//
61 304 tadejm
// Revision 1.53  2003/10/17 07:46:17  markom
62
// mbist signals updated according to newest convention
63
//
64 302 markom
// Revision 1.52  2003/01/30 14:51:31  mohor
65
// Reset has priority in some flipflops.
66
//
67 280 mohor
// Revision 1.51  2003/01/30 13:36:22  mohor
68
// A new bug (entered with previous update) fixed. When abort occured sometimes
69
// data transmission was blocked.
70
//
71 278 mohor
// Revision 1.50  2003/01/22 13:49:26  tadejm
72
// When control packets were received, they were ignored in some cases.
73
//
74 272 tadejm
// Revision 1.49  2003/01/21 12:09:40  mohor
75
// When receiving normal data frame and RxFlow control was switched on, RXB
76
// interrupt was not set.
77
//
78 270 mohor
// Revision 1.48  2003/01/20 12:05:26  mohor
79
// When in full duplex, transmit was sometimes blocked. Fixed.
80
//
81 269 mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
82
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
83
// anywhere. Removed.
84
//
85 264 mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
86
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
87
// synchronized.
88
//
89 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
90
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
91
// that a frame was received because of the promiscous mode.
92
//
93 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
94
// RxError is not generated when small frame reception is enabled and small
95
// frames are received.
96
//
97 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
98
// case changed to casex.
99
//
100 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
101
// Changed BIST scan signals.
102
//
103 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
104
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
105
//
106 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
107
// TxStatus is written after last access to the TX fifo is finished (in case of abort
108
// or retry). TxDone is fixed.
109
//
110 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
111
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
112
// TxDone and TxRetry are generated after the current WISHBONE access is
113
// finished.
114
//
115 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
116
// BIST added.
117
//
118 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
119
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
120
//
121 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
122
// Reception is possible after RxPointer is read and not after BD is read. For
123
// that reason RxBDReady is changed to RxReady.
124
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
125
// comes, interrupt is generated.
126
//
127 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
128
// Ethernet debug registers removed.
129
//
130 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
131
// Async reset for WB_ACK_O removed (when core was in reset, it was
132
// impossible to access BDs).
133
// RxPointers and TxPointers names changed to be more descriptive.
134
// TxUnderRun synchronized.
135
//
136 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
137
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
138
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
139
// was not used OK.
140
//
141 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
142
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
143
// need to multiply or devide any more.
144
//
145 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
146
// WriteRxDataToMemory signal changed so end of frame (when last word is
147
// written to fifo) is changed.
148
//
149 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
150
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
151
//
152 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
153
// ShiftEnded synchronization changed.
154
//
155 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
156
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
157
//
158 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
159
// RxPointer bug fixed.
160
//
161 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
162
// Previous bug wasn't succesfully removed. Now fixed.
163
//
164 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
165
// Master state machine had a bug when switching from master write to
166
// master read.
167
//
168 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
169
// m_wb_cyc_o signal released after every single transfer.
170
//
171 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
172
// Outputs registered. Reset changed for eth_wishbone module.
173
//
174 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
175
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
176
// bug fixed.
177
//
178 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
179
// Small typo fixed.
180
//
181 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
182
// Any address can be used for Tx and Rx BD pointers. Address does not need
183
// to be aligned.
184
//
185 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
186
// Comments in Slovene language removed.
187
//
188 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
189
// casex changed with case, fifo reset changed.
190
//
191 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
192
// rx_fifo was not always cleared ok. Fixed.
193
//
194 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
195
// Status was not latched correctly sometimes. Fixed.
196
//
197 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
198
// Big Endian problem when sending frames fixed.
199
//
200 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
201
// Byte ordering changed (Big Endian used). casex changed with case because
202
// Xilinx Foundation had problems. Tested in HW. It WORKS.
203
//
204 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
205
// Small fixes for external/internal DMA missmatches.
206
//
207 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
208
// Interrupts changed
209
//
210 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
211
// Status was not written correctly when frames were discarted because of
212
// address mismatch.
213
//
214 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
215
// RxStartFrm cleared when abort or retry comes.
216
//
217 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
218
// Changes that were lost when updating from 1.5 to 1.8 fixed.
219
//
220 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
221
// Addition  of new module eth_addrcheck.v
222
//
223
// Revision 1.7  2002/02/12 17:03:47  mohor
224
// RxOverRun added to statuses.
225
//
226
// Revision 1.6  2002/02/11 09:18:22  mohor
227
// Tx status is written back to the BD.
228
//
229 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
230
// Rx status is written back to the BD.
231
//
232 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
233
// non-DMA host interface added. Select the right configutation in eth_defines.
234
//
235 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
236
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
237
// MHz. Statuses, overrun, control frame transmission and reception still  need
238
// to be fixed.
239
//
240 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
241
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
242
// added.
243
//
244 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
245
// Initial version. Equals to eth_wishbonedma.v at this moment.
246 38 mohor
//
247
//
248
//
249
 
250 356 olof
`include "ethmac_defines.v"
251 38 mohor
`include "timescale.v"
252
 
253
 
254
module eth_wishbone
255 354 olof
  (
256 38 mohor
 
257 354 olof
   // WISHBONE common
258
   WB_CLK_I, WB_DAT_I, WB_DAT_O,
259 38 mohor
 
260 354 olof
   // WISHBONE slave
261
   WB_ADR_I, WB_WE_I, WB_ACK_O,
262
   BDCs,
263 38 mohor
 
264 354 olof
   Reset,
265 40 mohor
 
266 354 olof
   // WISHBONE master
267
   m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
268
   m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
269
   m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
270 39 mohor
 
271 219 mohor
`ifdef ETH_WISHBONE_B3
272 354 olof
   m_wb_cti_o, m_wb_bte_o,
273 219 mohor
`endif
274
 
275 354 olof
   //TX
276
   MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
277
   TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
278
   PerPacketPad,
279 38 mohor
 
280 354 olof
   //RX
281
   MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
282
   RxStatusWriteLatched_sync2,
283
 
284
   // Register
285
   r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
286 38 mohor
 
287 354 olof
   // Interrupts
288
   TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
289
 
290
   // Rx Status
291
   InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
292
   ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
293
   AddressMiss,
294
   ReceivedPauseFrm,
295
 
296
   // Tx Status
297
   RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched,
298
   CarrierSenseLost
299 164 mohor
 
300 354 olof
   // Bist
301 210 mohor
`ifdef ETH_BIST
302 354 olof
   ,
303
   // debug chain signals
304
   mbist_si_i,       // bist scan serial in
305
   mbist_so_o,       // bist scan serial out
306
   mbist_ctrl_i        // bist chain shift control
307 210 mohor
`endif
308
 
309
 
310 38 mohor
 
311 354 olof
   );
312 38 mohor
 
313 349 olof
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
314
parameter TX_FIFO_DEPTH      = `ETH_TX_FIFO_DEPTH;
315
parameter TX_FIFO_CNT_WIDTH  = `ETH_TX_FIFO_CNT_WIDTH;
316
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
317
parameter RX_FIFO_DEPTH      = `ETH_RX_FIFO_DEPTH;
318
parameter RX_FIFO_CNT_WIDTH  = `ETH_RX_FIFO_CNT_WIDTH;
319 38 mohor
 
320
// WISHBONE common
321
input           WB_CLK_I;       // WISHBONE clock
322
input  [31:0]   WB_DAT_I;       // WISHBONE data input
323
output [31:0]   WB_DAT_O;       // WISHBONE data output
324
 
325
// WISHBONE slave
326
input   [9:2]   WB_ADR_I;       // WISHBONE address input
327
input           WB_WE_I;        // WISHBONE write enable input
328 304 tadejm
input   [3:0]   BDCs;           // Buffer descriptors are selected
329 38 mohor
output          WB_ACK_O;       // WISHBONE acknowledge output
330
 
331 39 mohor
// WISHBONE master
332 329 igorm
output  [29:0]  m_wb_adr_o;     // 
333 39 mohor
output   [3:0]  m_wb_sel_o;     // 
334
output          m_wb_we_o;      // 
335
output  [31:0]  m_wb_dat_o;     // 
336
output          m_wb_cyc_o;     // 
337
output          m_wb_stb_o;     // 
338
input   [31:0]  m_wb_dat_i;     // 
339
input           m_wb_ack_i;     // 
340
input           m_wb_err_i;     // 
341
 
342 219 mohor
`ifdef ETH_WISHBONE_B3
343
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
344
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
345
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
346
`endif
347
 
348 40 mohor
input           Reset;       // Reset signal
349 39 mohor
 
350 60 mohor
// Rx Status signals
351 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
352
input           LatchedCrcError;  // CRC error
353
input           RxLateCollision;  // Late collision occured while receiving frame
354 354 olof
input           ShortFrame;       // Frame shorter then the minimum size
355
                                  // (r_MinFL) was received while small
356
                                  // packets are enabled (r_RecSmall)
357 42 mohor
input           DribbleNibble;    // Extra nibble received
358
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
359
input    [15:0] RxLength;         // Length of the incoming frame
360
input           LoadRxStatus;     // Rx status was loaded
361 354 olof
input           ReceivedPacketGood;  // Received packet's length and CRC are
362
                                     // good
363
input           AddressMiss;      // When a packet is received AddressMiss
364
                                  // status is written to the Rx BD
365 261 mohor
input           r_RxFlow;
366 270 mohor
input           r_PassAll;
367 261 mohor
input           ReceivedPauseFrm;
368 39 mohor
 
369 60 mohor
// Tx Status signals
370
input     [3:0] RetryCntLatched;  // Latched Retry Counter
371 354 olof
input           RetryLimit;       // Retry limit reached (Retry Max value +1
372
                                  // attempts were made)
373 60 mohor
input           LateCollLatched;  // Late collision occured
374 354 olof
input           DeferLatched;     // Defer indication (Frame was defered
375
                                  // before sucessfully sent)
376 329 igorm
output          RstDeferLatched;
377 354 olof
input           CarrierSenseLost; // Carrier Sense was lost during the
378
                                  // frame transmission
379 60 mohor
 
380 38 mohor
// Tx
381
input           MTxClk;         // Transmit clock (from PHY)
382
input           TxUsedData;     // Transmit packet used data
383
input           TxRetry;        // Transmit packet retry
384
input           TxAbort;        // Transmit packet abort
385
input           TxDone;         // Transmission ended
386
output          TxStartFrm;     // Transmit packet start frame
387
output          TxEndFrm;       // Transmit packet end frame
388
output  [7:0]   TxData;         // Transmit packet data byte
389
output          TxUnderRun;     // Transmit packet under-run
390
output          PerPacketCrcEn; // Per packet crc enable
391
output          PerPacketPad;   // Per packet pading
392
 
393
// Rx
394
input           MRxClk;         // Receive clock (from PHY)
395
input   [7:0]   RxData;         // Received data byte (from PHY)
396
input           RxValid;        // 
397
input           RxStartFrm;     // 
398
input           RxEndFrm;       // 
399 354 olof
input           RxAbort;        // This signal is set when address doesn't
400
                                // match.
401 272 tadejm
output          RxStatusWriteLatched_sync2;
402 38 mohor
 
403
//Register
404
input           r_TxEn;         // Transmit enable
405
input           r_RxEn;         // Receive enable
406
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
407
 
408
// Interrupts
409
output TxB_IRQ;
410
output TxE_IRQ;
411
output RxB_IRQ;
412 77 mohor
output RxE_IRQ;
413 38 mohor
output Busy_IRQ;
414
 
415 77 mohor
 
416 210 mohor
// Bist
417
`ifdef ETH_BIST
418 302 markom
input   mbist_si_i;       // bist scan serial in
419
output  mbist_so_o;       // bist scan serial out
420 354 olof
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
421 210 mohor
`endif
422
 
423 77 mohor
reg TxB_IRQ;
424
reg TxE_IRQ;
425
reg RxB_IRQ;
426
reg RxE_IRQ;
427
 
428 38 mohor
reg             TxStartFrm;
429
reg             TxEndFrm;
430
reg     [7:0]   TxData;
431
 
432
reg             TxUnderRun;
433 60 mohor
reg             TxUnderRun_wb;
434 38 mohor
 
435
reg             TxBDRead;
436 39 mohor
wire            TxStatusWrite;
437 38 mohor
 
438
reg     [1:0]   TxValidBytesLatched;
439
 
440
reg    [15:0]   TxLength;
441 60 mohor
reg    [15:0]   LatchedTxLength;
442
reg   [14:11]   TxStatus;
443 38 mohor
 
444 60 mohor
reg   [14:13]   RxStatus;
445 38 mohor
 
446
reg             TxStartFrm_wb;
447
reg             TxRetry_wb;
448 39 mohor
reg             TxAbort_wb;
449 38 mohor
reg             TxDone_wb;
450
 
451
reg             TxDone_wb_q;
452
reg             TxAbort_wb_q;
453 39 mohor
reg             TxRetry_wb_q;
454 219 mohor
reg             TxRetryPacket;
455 221 mohor
reg             TxRetryPacket_NotCleared;
456
reg             TxDonePacket;
457
reg             TxDonePacket_NotCleared;
458 219 mohor
reg             TxAbortPacket;
459 221 mohor
reg             TxAbortPacket_NotCleared;
460 38 mohor
reg             RxBDReady;
461 166 mohor
reg             RxReady;
462 38 mohor
reg             TxBDReady;
463
 
464
reg             RxBDRead;
465
 
466
reg    [31:0]   TxDataLatched;
467
reg     [1:0]   TxByteCnt;
468
reg             LastWord;
469 39 mohor
reg             ReadTxDataFromFifo_tck;
470 38 mohor
 
471
reg             BlockingTxStatusWrite;
472
reg             BlockingTxBDRead;
473
 
474 40 mohor
reg             Flop;
475 38 mohor
 
476 329 igorm
reg     [7:1]   TxBDAddress;
477
reg     [7:1]   RxBDAddress;
478 38 mohor
 
479
reg             TxRetrySync1;
480
reg             TxAbortSync1;
481 39 mohor
reg             TxDoneSync1;
482 38 mohor
 
483
reg             TxAbort_q;
484
reg             TxRetry_q;
485
reg             TxUsedData_q;
486
 
487
reg    [31:0]   RxDataLatched2;
488 82 mohor
 
489
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
490
 
491 38 mohor
reg     [1:0]   RxValidBytes;
492
reg     [1:0]   RxByteCnt;
493
reg             LastByteIn;
494
reg             ShiftWillEnd;
495
 
496 40 mohor
reg             WriteRxDataToFifo;
497 42 mohor
reg    [15:0]   LatchedRxLength;
498 64 mohor
reg             RxAbortLatched;
499 38 mohor
 
500 40 mohor
reg             ShiftEnded;
501 60 mohor
reg             RxOverrun;
502 38 mohor
 
503 304 tadejm
reg     [3:0]   BDWrite;                    // BD Write Enable for access from WISHBONE side
504 40 mohor
reg             BDRead;                     // BD Read access from WISHBONE side
505 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
506
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
507 38 mohor
 
508 39 mohor
reg             TxEndFrm_wb;
509 38 mohor
 
510 39 mohor
wire            TxRetryPulse;
511 38 mohor
wire            TxDonePulse;
512
wire            TxAbortPulse;
513
 
514
wire            StartRxBDRead;
515
 
516
wire            StartTxBDRead;
517
 
518
wire            TxIRQEn;
519
wire            WrapTxStatusBit;
520
 
521 77 mohor
wire            RxIRQEn;
522 38 mohor
wire            WrapRxStatusBit;
523
 
524
wire    [1:0]   TxValidBytes;
525
 
526 329 igorm
wire    [7:1]   TempTxBDAddress;
527
wire    [7:1]   TempRxBDAddress;
528 38 mohor
 
529 272 tadejm
wire            RxStatusWrite;
530 329 igorm
wire            RxBufferFull;
531
wire            RxBufferAlmostEmpty;
532
wire            RxBufferEmpty;
533 272 tadejm
 
534 106 mohor
reg             WB_ACK_O;
535 38 mohor
 
536 261 mohor
wire    [8:0]   RxStatusIn;
537
reg     [8:0]   RxStatusInLatched;
538 42 mohor
 
539 39 mohor
reg WbEn, WbEn_q;
540
reg RxEn, RxEn_q;
541
reg TxEn, TxEn_q;
542 321 igorm
reg r_TxEn_q;
543
reg r_RxEn_q;
544 38 mohor
 
545 39 mohor
wire ram_ce;
546 304 tadejm
wire [3:0]  ram_we;
547 39 mohor
wire ram_oe;
548
reg [7:0]   ram_addr;
549
reg [31:0]  ram_di;
550
wire [31:0] ram_do;
551 38 mohor
 
552 39 mohor
wire StartTxPointerRead;
553 354 olof
reg TxPointerRead;
554 39 mohor
reg TxEn_needed;
555 40 mohor
reg RxEn_needed;
556 38 mohor
 
557 40 mohor
wire StartRxPointerRead;
558 355 olof
reg RxPointerRead;
559 38 mohor
 
560 354 olof
// RX shift ending signals
561
reg ShiftEnded_rck;
562
reg ShiftEndedSync1;
563
reg ShiftEndedSync2;
564
reg ShiftEndedSync3;
565
reg ShiftEndedSync_c1;
566
reg ShiftEndedSync_c2;
567
 
568
wire StartShiftWillEnd;
569
 
570
reg StartOccured;
571
reg TxStartFrm_sync1;
572
reg TxStartFrm_sync2;
573
reg TxStartFrm_syncb1;
574
reg TxStartFrm_syncb2;
575
 
576
wire TxFifoClear;
577
wire TxBufferAlmostFull;
578
wire TxBufferFull;
579
wire TxBufferEmpty;
580
wire TxBufferAlmostEmpty;
581
wire SetReadTxDataFromMemory;
582
reg BlockReadTxDataFromMemory;
583
 
584
reg tx_burst_en;
585
reg rx_burst_en;
586
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
587
 
588
wire ReadTxDataFromMemory_2;
589
wire tx_burst;
590
 
591
wire [31:0] TxData_wb;
592
wire ReadTxDataFromFifo_wb;
593
 
594
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
595
wire [RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
596
 
597
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
598
 
599
wire rx_burst;
600
wire enough_data_in_rxfifo_for_burst;
601
wire enough_data_in_rxfifo_for_burst_plus1;
602
 
603
reg ReadTxDataFromMemory;
604
wire WriteRxDataToMemory;
605
 
606
reg MasterWbTX;
607
reg MasterWbRX;
608
 
609
reg [29:0] m_wb_adr_o;
610
reg        m_wb_cyc_o;
611
reg  [3:0] m_wb_sel_o;
612
reg        m_wb_we_o;
613
 
614
wire TxLengthEq0;
615
wire TxLengthLt4;
616
 
617
reg BlockingIncrementTxPointer;
618
reg [31:2] TxPointerMSB;
619
reg [1:0]  TxPointerLSB;
620
reg [1:0]  TxPointerLSB_rst;
621
reg [31:2] RxPointerMSB;
622
reg [1:0]  RxPointerLSB_rst;
623
 
624
wire RxBurstAcc;
625
wire RxWordAcc;
626
wire RxHalfAcc;
627
wire RxByteAcc;
628
 
629
wire ResetTxBDReady;
630
reg BlockingTxStatusWrite_sync1;
631
reg BlockingTxStatusWrite_sync2;
632
reg BlockingTxStatusWrite_sync3;
633
 
634
reg cyc_cleared;
635
reg IncrTxPointer;
636
 
637
reg  [3:0] RxByteSel;
638
wire MasterAccessFinished;
639
 
640
reg LatchValidBytes;
641
reg LatchValidBytes_q;
642
 
643
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
644
reg ReadTxDataFromFifo_sync1;
645
reg ReadTxDataFromFifo_sync2;
646
reg ReadTxDataFromFifo_sync3;
647
reg ReadTxDataFromFifo_syncb1;
648
reg ReadTxDataFromFifo_syncb2;
649
reg ReadTxDataFromFifo_syncb3;
650
 
651
reg RxAbortSync1;
652
reg RxAbortSync2;
653
reg RxAbortSync3;
654
reg RxAbortSync4;
655
reg RxAbortSyncb1;
656
reg RxAbortSyncb2;
657
 
658
reg RxEnableWindow;
659
 
660
wire SetWriteRxDataToFifo;
661
 
662
reg WriteRxDataToFifoSync1;
663
reg WriteRxDataToFifoSync2;
664
reg WriteRxDataToFifoSync3;
665
 
666
wire WriteRxDataToFifo_wb;
667
 
668
reg LatchedRxStartFrm;
669
reg SyncRxStartFrm;
670
reg SyncRxStartFrm_q;
671
reg SyncRxStartFrm_q2;
672
wire RxFifoReset;
673
 
674
wire TxError;
675
wire RxError;
676
 
677
reg RxStatusWriteLatched;
678
reg RxStatusWriteLatched_sync1;
679
reg RxStatusWriteLatched_sync2;
680
reg RxStatusWriteLatched_syncb1;
681
reg RxStatusWriteLatched_syncb2;
682
 
683 219 mohor
`ifdef ETH_WISHBONE_B3
684
assign m_wb_bte_o = 2'b00;    // Linear burst
685
`endif
686 39 mohor
 
687 329 igorm
assign m_wb_stb_o = m_wb_cyc_o;
688 219 mohor
 
689 159 mohor
always @ (posedge WB_CLK_I)
690 40 mohor
begin
691 352 olof
  WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
692 40 mohor
end
693 39 mohor
 
694 106 mohor
assign WB_DAT_O = ram_do;
695 39 mohor
 
696 41 mohor
// Generic synchronous single-port RAM interface
697 354 olof
eth_spram_256x32
698
     bd_ram
699
     (
700
      .clk     (WB_CLK_I),
701
      .rst     (Reset),
702
      .ce      (ram_ce),
703
      .we      (ram_we),
704
      .oe      (ram_oe),
705
      .addr    (ram_addr),
706
      .di      (ram_di),
707
      .do      (ram_do)
708 210 mohor
`ifdef ETH_BIST
709 354 olof
      ,
710
      .mbist_si_i       (mbist_si_i),
711
      .mbist_so_o       (mbist_so_o),
712
      .mbist_ctrl_i       (mbist_ctrl_i)
713 210 mohor
`endif
714 354 olof
      );
715 41 mohor
 
716 39 mohor
assign ram_ce = 1'b1;
717 354 olof
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) |
718
                {4{(TxStatusWrite | RxStatusWrite)}};
719
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q &
720
                (TxBDRead | TxPointerRead) | RxEn & RxEn_q &
721
                (RxBDRead | RxPointerRead);
722 39 mohor
 
723
 
724 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
725 38 mohor
begin
726 40 mohor
  if(Reset)
727 352 olof
    TxEn_needed <= 1'b0;
728 38 mohor
  else
729 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
730 352 olof
    TxEn_needed <= 1'b1;
731 39 mohor
  else
732
  if(TxPointerRead & TxEn & TxEn_q)
733 352 olof
    TxEn_needed <= 1'b0;
734 38 mohor
end
735
 
736 39 mohor
// Enabling access to the RAM for three devices.
737 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
738 39 mohor
begin
739 40 mohor
  if(Reset)
740 39 mohor
    begin
741 352 olof
      WbEn <= 1'b1;
742
      RxEn <= 1'b0;
743
      TxEn <= 1'b0;
744
      ram_addr <= 8'h0;
745
      ram_di <= 32'h0;
746
      BDRead <= 1'b0;
747
      BDWrite <= 1'b0;
748 39 mohor
    end
749
  else
750
    begin
751
      // Switching between three stages depends on enable signals
752 355 olof
     /* verilator lint_off CASEINCOMPLETE */ // JB
753 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
754
        5'b100_10, 5'b100_11 :
755 39 mohor
          begin
756 352 olof
            WbEn <= 1'b0;
757
            RxEn <= 1'b1;  // wb access stage and r_RxEn is enabled
758
            TxEn <= 1'b0;
759
            ram_addr <= {RxBDAddress, RxPointerRead};
760
            ram_di <= RxBDDataIn;
761 39 mohor
          end
762
        5'b100_01 :
763
          begin
764 352 olof
            WbEn <= 1'b0;
765
            RxEn <= 1'b0;
766 354 olof
            TxEn <= 1'b1;  // wb access stage, r_RxEn is disabled but
767
                           // r_TxEn is enabled
768 352 olof
            ram_addr <= {TxBDAddress, TxPointerRead};
769
            ram_di <= TxBDDataIn;
770 39 mohor
          end
771 90 mohor
        5'b010_00, 5'b010_10 :
772 39 mohor
          begin
773 352 olof
            WbEn <= 1'b1;  // RxEn access stage and r_TxEn is disabled
774
            RxEn <= 1'b0;
775
            TxEn <= 1'b0;
776
            ram_addr <= WB_ADR_I[9:2];
777
            ram_di <= WB_DAT_I;
778
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
779
            BDRead <= (|BDCs) & ~WB_WE_I;
780 39 mohor
          end
781 90 mohor
        5'b010_01, 5'b010_11 :
782 39 mohor
          begin
783 352 olof
            WbEn <= 1'b0;
784
            RxEn <= 1'b0;
785
            TxEn <= 1'b1;  // RxEn access stage and r_TxEn is enabled
786
            ram_addr <= {TxBDAddress, TxPointerRead};
787
            ram_di <= TxBDDataIn;
788 39 mohor
          end
789 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
790 39 mohor
          begin
791 354 olof
            WbEn <= 1'b1;  // TxEn access stage (we always go to wb
792
                           // access stage)
793 352 olof
            RxEn <= 1'b0;
794
            TxEn <= 1'b0;
795
            ram_addr <= WB_ADR_I[9:2];
796
            ram_di <= WB_DAT_I;
797
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
798
            BDRead <= (|BDCs) & ~WB_WE_I;
799 39 mohor
          end
800
        5'b100_00 :
801
          begin
802 354 olof
            WbEn <= 1'b0;  // WbEn access stage and there is no need
803
                           // for other stages. WbEn needs to be
804
                           // switched off for a bit
805 39 mohor
          end
806
        5'b000_00 :
807
          begin
808 352 olof
            WbEn <= 1'b1;  // Idle state. We go to WbEn access stage.
809
            RxEn <= 1'b0;
810
            TxEn <= 1'b0;
811
            ram_addr <= WB_ADR_I[9:2];
812
            ram_di <= WB_DAT_I;
813
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
814
            BDRead <= (|BDCs) & ~WB_WE_I;
815 39 mohor
          end
816
      endcase
817 355 olof
      /* verilator lint_on CASEINCOMPLETE */
818 39 mohor
    end
819
end
820
 
821
 
822
// Delayed stage signals
823 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
824 39 mohor
begin
825 40 mohor
  if(Reset)
826 39 mohor
    begin
827 352 olof
      WbEn_q <= 1'b0;
828
      RxEn_q <= 1'b0;
829
      TxEn_q <= 1'b0;
830
      r_TxEn_q <= 1'b0;
831
      r_RxEn_q <= 1'b0;
832 39 mohor
    end
833
  else
834
    begin
835 352 olof
      WbEn_q <= WbEn;
836
      RxEn_q <= RxEn;
837
      TxEn_q <= TxEn;
838
      r_TxEn_q <= r_TxEn;
839
      r_RxEn_q <= r_RxEn;
840 39 mohor
    end
841
end
842
 
843 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
844 40 mohor
always @ (posedge MTxClk or posedge Reset)
845 38 mohor
begin
846 40 mohor
  if(Reset)
847 352 olof
    Flop <= 1'b0;
848 38 mohor
  else
849
  if(TxDone | TxAbort | TxRetry_q)
850 352 olof
    Flop <= 1'b0;
851 38 mohor
  else
852
  if(TxUsedData)
853 352 olof
    Flop <= ~Flop;
854 38 mohor
end
855
 
856 39 mohor
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
857 38 mohor
 
858
// Latching READY status of the Tx buffer descriptor
859 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
860 38 mohor
begin
861 40 mohor
  if(Reset)
862 352 olof
    TxBDReady <= 1'b0;
863 38 mohor
  else
864 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
865 354 olof
    // TxBDReady is sampled only once at the beginning.
866
    TxBDReady <= ram_do[15] & (ram_do[31:16] > 4);
867
  else
868
  // Only packets larger then 4 bytes are transmitted.
869 39 mohor
  if(ResetTxBDReady)
870 352 olof
    TxBDReady <= 1'b0;
871 38 mohor
end
872
 
873 39 mohor
// Reading the Tx buffer descriptor
874 354 olof
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) &
875
                       ~BlockingTxBDRead & ~TxBDReady;
876 39 mohor
 
877 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
878 38 mohor
begin
879 40 mohor
  if(Reset)
880 352 olof
    TxBDRead <= 1'b1;
881 38 mohor
  else
882 110 mohor
  if(StartTxBDRead)
883 352 olof
    TxBDRead <= 1'b1;
884 38 mohor
  else
885 39 mohor
  if(TxBDReady)
886 352 olof
    TxBDRead <= 1'b0;
887 38 mohor
end
888
 
889 39 mohor
// Reading Tx BD pointer
890
assign StartTxPointerRead = TxBDRead & TxBDReady;
891 38 mohor
 
892 39 mohor
// Reading Tx BD Pointer
893 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
894 38 mohor
begin
895 40 mohor
  if(Reset)
896 352 olof
    TxPointerRead <= 1'b0;
897 38 mohor
  else
898 39 mohor
  if(StartTxPointerRead)
899 352 olof
    TxPointerRead <= 1'b1;
900 38 mohor
  else
901 39 mohor
  if(TxEn_q)
902 352 olof
    TxPointerRead <= 1'b0;
903 38 mohor
end
904
 
905
 
906 39 mohor
// Writing status back to the Tx buffer descriptor
907 354 olof
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) &
908
                       TxEn & TxEn_q & ~BlockingTxStatusWrite;
909 38 mohor
 
910
 
911 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
912 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
913 38 mohor
begin
914 40 mohor
  if(Reset)
915 352 olof
    BlockingTxStatusWrite <= 1'b0;
916 38 mohor
  else
917 272 tadejm
  if(~TxDone_wb & ~TxAbort_wb)
918 352 olof
    BlockingTxStatusWrite <= 1'b0;
919 272 tadejm
  else
920 39 mohor
  if(TxStatusWrite)
921 352 olof
    BlockingTxStatusWrite <= 1'b1;
922 38 mohor
end
923
 
924
 
925 159 mohor
// Synchronizing BlockingTxStatusWrite to MTxClk
926
always @ (posedge MTxClk or posedge Reset)
927
begin
928
  if(Reset)
929 352 olof
    BlockingTxStatusWrite_sync1 <= 1'b0;
930 159 mohor
  else
931 352 olof
    BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite;
932 159 mohor
end
933
 
934
// Synchronizing BlockingTxStatusWrite to MTxClk
935
always @ (posedge MTxClk or posedge Reset)
936
begin
937
  if(Reset)
938 352 olof
    BlockingTxStatusWrite_sync2 <= 1'b0;
939 159 mohor
  else
940 352 olof
    BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1;
941 159 mohor
end
942
 
943 329 igorm
// Synchronizing BlockingTxStatusWrite to MTxClk
944
always @ (posedge MTxClk or posedge Reset)
945
begin
946
  if(Reset)
947 352 olof
    BlockingTxStatusWrite_sync3 <= 1'b0;
948 329 igorm
  else
949 352 olof
    BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2;
950 329 igorm
end
951 159 mohor
 
952 354 olof
assign RstDeferLatched = BlockingTxStatusWrite_sync2 &
953
                         ~BlockingTxStatusWrite_sync3;
954 329 igorm
 
955 39 mohor
// TxBDRead state is activated only once. 
956 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
957 39 mohor
begin
958 40 mohor
  if(Reset)
959 352 olof
    BlockingTxBDRead <= 1'b0;
960 39 mohor
  else
961 110 mohor
  if(StartTxBDRead)
962 352 olof
    BlockingTxBDRead <= 1'b1;
963 39 mohor
  else
964 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
965 352 olof
    BlockingTxBDRead <= 1'b0;
966 39 mohor
end
967 38 mohor
 
968
 
969 39 mohor
// Latching status from the tx buffer descriptor
970 354 olof
// Data is avaliable one cycle after the access is started (at that time
971
// signal TxEn is not active)
972 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
973 38 mohor
begin
974 40 mohor
  if(Reset)
975 352 olof
    TxStatus <= 4'h0;
976 38 mohor
  else
977 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
978 352 olof
    TxStatus <= ram_do[14:11];
979 38 mohor
end
980
 
981
 
982 39 mohor
 
983
//Latching length from the buffer descriptor;
984 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
985 38 mohor
begin
986 40 mohor
  if(Reset)
987 352 olof
    TxLength <= 16'h0;
988 38 mohor
  else
989 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
990 352 olof
    TxLength <= ram_do[31:16];
991 38 mohor
  else
992 39 mohor
  if(MasterWbTX & m_wb_ack_i)
993
    begin
994
      if(TxLengthLt4)
995 352 olof
        TxLength <= 16'h0;
996 354 olof
      else if(TxPointerLSB_rst==2'h0)
997
        TxLength <= TxLength - 3'h4;    // Length is subtracted at
998
                                        // the data request
999
      else if(TxPointerLSB_rst==2'h1)
1000
        TxLength <= TxLength - 3'h3;     // Length is subtracted
1001
                                         // at the data request
1002
      else if(TxPointerLSB_rst==2'h2)
1003
        TxLength <= TxLength - 3'h2;     // Length is subtracted
1004
                                         // at the data request
1005
      else if(TxPointerLSB_rst==2'h3)
1006
        TxLength <= TxLength - 3'h1;     // Length is subtracted
1007
                                         // at the data request
1008 39 mohor
    end
1009 38 mohor
end
1010
 
1011 60 mohor
//Latching length from the buffer descriptor;
1012
always @ (posedge WB_CLK_I or posedge Reset)
1013
begin
1014
  if(Reset)
1015 352 olof
    LatchedTxLength <= 16'h0;
1016 60 mohor
  else
1017
  if(TxEn & TxEn_q & TxBDRead)
1018 352 olof
    LatchedTxLength <= ram_do[31:16];
1019 60 mohor
end
1020
 
1021 39 mohor
assign TxLengthEq0 = TxLength == 0;
1022
assign TxLengthLt4 = TxLength < 4;
1023 38 mohor
 
1024 39 mohor
 
1025 354 olof
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are
1026
// latched because TxPointerMSB is only used for word-aligned accesses.
1027 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1028 38 mohor
begin
1029 40 mohor
  if(Reset)
1030 352 olof
    TxPointerMSB <= 30'h0;
1031 38 mohor
  else
1032 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
1033 352 olof
    TxPointerMSB <= ram_do[31:2];
1034 38 mohor
  else
1035 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
1036 354 olof
      // TxPointer is word-aligned
1037
    TxPointerMSB <= TxPointerMSB + 1'b1;
1038 38 mohor
end
1039
 
1040 96 mohor
 
1041 354 olof
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are
1042
// performed, valid data does not necesserly start at byte 0 (could be byte
1043
// 0, 1, 2 or 3). This signals are used for proper selection of the start
1044
// byte (TxData and TxByteCnt) are set by this two bits.
1045 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1046
begin
1047
  if(Reset)
1048 352 olof
    TxPointerLSB[1:0] <= 0;
1049 96 mohor
  else
1050
  if(TxEn & TxEn_q & TxPointerRead)
1051 352 olof
    TxPointerLSB[1:0] <= ram_do[1:0];
1052 96 mohor
end
1053
 
1054
 
1055 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
1056 354 olof
// After the read access, TxLength needs to be decremented for the number of
1057
// the valid bytes (1 to 4 bytes are valid in the first word). After the
1058
// first read all bytes are valid so this two bits are reset to zero. 
1059 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1060
begin
1061
  if(Reset)
1062 352 olof
    TxPointerLSB_rst[1:0] <= 0;
1063 150 mohor
  else
1064
  if(TxEn & TxEn_q & TxPointerRead)
1065 352 olof
    TxPointerLSB_rst[1:0] <= ram_do[1:0];
1066 150 mohor
  else
1067 354 olof
// After first access pointer is word alligned
1068
  if(MasterWbTX & m_wb_ack_i)
1069 352 olof
    TxPointerLSB_rst[1:0] <= 0;
1070 150 mohor
end
1071 96 mohor
 
1072 150 mohor
 
1073 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1074 38 mohor
begin
1075 40 mohor
  if(Reset)
1076 352 olof
    BlockingIncrementTxPointer <= 0;
1077 38 mohor
  else
1078 39 mohor
  if(MasterAccessFinished)
1079 352 olof
    BlockingIncrementTxPointer <= 0;
1080 38 mohor
  else
1081 150 mohor
  if(IncrTxPointer)
1082 352 olof
    BlockingIncrementTxPointer <= 1'b1;
1083 38 mohor
end
1084
 
1085
 
1086 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
1087 39 mohor
 
1088 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1089 38 mohor
begin
1090 40 mohor
  if(Reset)
1091 352 olof
    ReadTxDataFromMemory <= 1'b0;
1092 38 mohor
  else
1093 278 mohor
  if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
1094 352 olof
    ReadTxDataFromMemory <= 1'b0;
1095 39 mohor
  else
1096 40 mohor
  if(SetReadTxDataFromMemory)
1097 352 olof
    ReadTxDataFromMemory <= 1'b1;
1098 38 mohor
end
1099
 
1100 354 olof
assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory &
1101
                                ~BlockReadTxDataFromMemory;
1102 221 mohor
 
1103 354 olof
assign tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
1104 221 mohor
 
1105 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1106 38 mohor
begin
1107 40 mohor
  if(Reset)
1108 352 olof
    BlockReadTxDataFromMemory <= 1'b0;
1109 38 mohor
  else
1110 354 olof
  if((TxBufferAlmostFull | TxLength <= 4) & MasterWbTX & (~cyc_cleared) &
1111
     (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
1112 352 olof
    BlockReadTxDataFromMemory <= 1'b1;
1113 219 mohor
  else
1114 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
1115 352 olof
    BlockReadTxDataFromMemory <= 1'b0;
1116 39 mohor
end
1117
 
1118
 
1119
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
1120 159 mohor
 
1121 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
1122 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1123 39 mohor
begin
1124 40 mohor
  if(Reset)
1125 38 mohor
    begin
1126 352 olof
      MasterWbTX <= 1'b0;
1127
      MasterWbRX <= 1'b0;
1128
      m_wb_adr_o <= 30'h0;
1129
      m_wb_cyc_o <= 1'b0;
1130
      m_wb_we_o  <= 1'b0;
1131
      m_wb_sel_o <= 4'h0;
1132
      cyc_cleared<= 1'b0;
1133
      tx_burst_cnt<= 0;
1134
      rx_burst_cnt<= 0;
1135
      IncrTxPointer<= 1'b0;
1136
      tx_burst_en<= 1'b1;
1137
      rx_burst_en<= 1'b0;
1138 354 olof
`ifdef ETH_WISHBONE_B3
1139
      m_wb_cti_o <= 3'b0;
1140
`endif
1141 38 mohor
    end
1142 39 mohor
  else
1143
    begin
1144
      // Switching between two stages depends on enable signals
1145 354 olof
      casex ({MasterWbTX,
1146
             MasterWbRX,
1147
             ReadTxDataFromMemory_2,
1148
             WriteRxDataToMemory,
1149
             MasterAccessFinished,
1150
             cyc_cleared,
1151
             tx_burst,
1152
             rx_burst})  // synopsys parallel_case
1153
 
1154
        8'b00_10_00_10, // Idle and MRB needed
1155
        8'b10_1x_10_1x, // MRB continues
1156
        8'b10_10_01_10, // Clear (previously MR) and MRB needed
1157
        8'b01_1x_01_1x :// Clear (previously MW) and MRB needed
1158 39 mohor
          begin
1159 352 olof
            MasterWbTX <= 1'b1;  // tx burst
1160
            MasterWbRX <= 1'b0;
1161
            m_wb_cyc_o <= 1'b1;
1162
            m_wb_we_o  <= 1'b0;
1163
            m_wb_sel_o <= 4'hf;
1164
            cyc_cleared<= 1'b0;
1165
            IncrTxPointer<= 1'b1;
1166
            tx_burst_cnt <= tx_burst_cnt+3'h1;
1167 226 tadejm
            if(tx_burst_cnt==0)
1168 352 olof
              m_wb_adr_o <= TxPointerMSB;
1169 226 tadejm
            else
1170 354 olof
              m_wb_adr_o <= m_wb_adr_o + 1'b1;
1171 226 tadejm
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1172
              begin
1173 352 olof
                tx_burst_en<= 1'b0;
1174 354 olof
`ifdef ETH_WISHBONE_B3
1175 352 olof
                m_wb_cti_o <= 3'b111;
1176 354 olof
`endif
1177 226 tadejm
              end
1178
            else
1179
              begin
1180 354 olof
`ifdef ETH_WISHBONE_B3
1181 352 olof
                m_wb_cti_o <= 3'b010;
1182 354 olof
`endif
1183 226 tadejm
              end
1184
          end
1185 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1186
        8'b01_x1_10_x1,             // MWB continues
1187 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1188 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1189 226 tadejm
          begin
1190 352 olof
            MasterWbTX <= 1'b0;  // rx burst
1191
            MasterWbRX <= 1'b1;
1192
            m_wb_cyc_o <= 1'b1;
1193
            m_wb_we_o  <= 1'b1;
1194
            m_wb_sel_o <= RxByteSel;
1195
            IncrTxPointer<= 1'b0;
1196
            cyc_cleared<= 1'b0;
1197
            rx_burst_cnt <= rx_burst_cnt+3'h1;
1198 226 tadejm
 
1199
            if(rx_burst_cnt==0)
1200 352 olof
              m_wb_adr_o <= RxPointerMSB;
1201 226 tadejm
            else
1202 352 olof
              m_wb_adr_o <= m_wb_adr_o+1'b1;
1203 226 tadejm
 
1204
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1205
              begin
1206 352 olof
                rx_burst_en<= 1'b0;
1207 354 olof
 `ifdef ETH_WISHBONE_B3
1208 352 olof
                m_wb_cti_o <= 3'b111;
1209 354 olof
 `endif
1210 226 tadejm
              end
1211
            else
1212
              begin
1213 354 olof
 `ifdef ETH_WISHBONE_B3
1214 352 olof
                m_wb_cti_o <= 3'b010;
1215 354 olof
 `endif
1216 226 tadejm
              end
1217
          end
1218 354 olof
        8'b00_x1_00_x0 :// idle and MW is needed (data write to rx buffer)
1219 226 tadejm
          begin
1220 352 olof
            MasterWbTX <= 1'b0;
1221
            MasterWbRX <= 1'b1;
1222
            m_wb_adr_o <= RxPointerMSB;
1223
            m_wb_cyc_o <= 1'b1;
1224
            m_wb_we_o  <= 1'b1;
1225
            m_wb_sel_o <= RxByteSel;
1226
            IncrTxPointer<= 1'b0;
1227 39 mohor
          end
1228 354 olof
        8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
1229 39 mohor
          begin
1230 352 olof
            MasterWbTX <= 1'b1;
1231
            MasterWbRX <= 1'b0;
1232
            m_wb_adr_o <= TxPointerMSB;
1233
            m_wb_cyc_o <= 1'b1;
1234
            m_wb_we_o  <= 1'b0;
1235
            m_wb_sel_o <= 4'hf;
1236
            IncrTxPointer<= 1'b1;
1237 39 mohor
          end
1238 354 olof
        8'b10_10_01_00,// MR and MR is needed (data read from tx buffer)
1239
        8'b01_1x_01_0x  :// MW and MR is needed (data read from tx buffer)
1240 39 mohor
          begin
1241 352 olof
            MasterWbTX <= 1'b1;
1242
            MasterWbRX <= 1'b0;
1243
            m_wb_adr_o <= TxPointerMSB;
1244
            m_wb_cyc_o <= 1'b1;
1245
            m_wb_we_o  <= 1'b0;
1246
            m_wb_sel_o <= 4'hf;
1247
            cyc_cleared<= 1'b0;
1248
            IncrTxPointer<= 1'b1;
1249 39 mohor
          end
1250 354 olof
        8'b01_01_01_00,// MW and MW needed (data write to rx buffer)
1251
        8'b10_x1_01_x0  :// MR and MW is needed (data write to rx buffer)
1252 39 mohor
          begin
1253 352 olof
            MasterWbTX <= 1'b0;
1254
            MasterWbRX <= 1'b1;
1255
            m_wb_adr_o <= RxPointerMSB;
1256
            m_wb_cyc_o <= 1'b1;
1257
            m_wb_we_o  <= 1'b1;
1258
            m_wb_sel_o <= RxByteSel;
1259
            cyc_cleared<= 1'b0;
1260
            IncrTxPointer<= 1'b0;
1261 39 mohor
          end
1262 354 olof
        8'b01_01_10_00,// MW and MW needed (cycle is cleared between
1263
                      // previous and next access)
1264
        8'b01_1x_10_x0,// MW and MW or MR or MRB needed (cycle is
1265
                    // cleared between previous and next access)
1266
        8'b10_10_10_00,// MR and MR needed (cycle is cleared between
1267
                       // previous and next access)
1268
        8'b10_x1_10_0x :// MR and MR or MW or MWB (cycle is cleared
1269
                       // between previous and next access)
1270 39 mohor
          begin
1271 354 olof
            m_wb_cyc_o <= 1'b0;// whatever and master read or write is
1272
                               // needed. We need to clear m_wb_cyc_o
1273
                               // before next access is started
1274 352 olof
            cyc_cleared<= 1'b1;
1275
            IncrTxPointer<= 1'b0;
1276
            tx_burst_cnt<= 0;
1277
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1278
            rx_burst_cnt<= 0;
1279
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1280 354 olof
`ifdef ETH_WISHBONE_B3
1281 352 olof
              m_wb_cti_o <= 3'b0;
1282 354 olof
`endif
1283 110 mohor
          end
1284 354 olof
        8'bxx_00_10_00,// whatever and no master read or write is needed
1285
                       // (ack or err comes finishing previous access)
1286
        8'bxx_00_01_00 : // Between cyc_cleared request was cleared
1287 110 mohor
          begin
1288 352 olof
            MasterWbTX <= 1'b0;
1289
            MasterWbRX <= 1'b0;
1290
            m_wb_cyc_o <= 1'b0;
1291
            cyc_cleared<= 1'b0;
1292
            IncrTxPointer<= 1'b0;
1293
            rx_burst_cnt<= 0;
1294 354 olof
            // Counter is not decremented, yet, so plus1 is used.
1295
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 :
1296
                                       enough_data_in_rxfifo_for_burst;
1297
`ifdef ETH_WISHBONE_B3
1298
            m_wb_cti_o <= 3'b0;
1299
`endif
1300 39 mohor
          end
1301 354 olof
        8'b00_00_00_00:  // whatever and no master read or write is needed
1302
                         // (ack or err comes finishing previous access)
1303 127 mohor
          begin
1304 352 olof
            tx_burst_cnt<= 0;
1305
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1306 127 mohor
          end
1307 226 tadejm
        default:                    // Don't touch
1308 82 mohor
          begin
1309 352 olof
            MasterWbTX <= MasterWbTX;
1310
            MasterWbRX <= MasterWbRX;
1311
            m_wb_cyc_o <= m_wb_cyc_o;
1312
            m_wb_sel_o <= m_wb_sel_o;
1313
            IncrTxPointer<= IncrTxPointer;
1314 82 mohor
          end
1315 39 mohor
      endcase
1316
    end
1317 38 mohor
end
1318
 
1319 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1320 38 mohor
 
1321 354 olof
eth_fifo
1322
     #(
1323
       .DATA_WIDTH(TX_FIFO_DATA_WIDTH),
1324
       .DEPTH(TX_FIFO_DEPTH),
1325
       .CNT_WIDTH(TX_FIFO_CNT_WIDTH))
1326
tx_fifo (
1327
       .data_in(m_wb_dat_i),
1328
       .data_out(TxData_wb),
1329
       .clk(WB_CLK_I),
1330
       .reset(Reset),
1331
       .write(MasterWbTX & m_wb_ack_i),
1332
       .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1333
       .clear(TxFifoClear),
1334
       .full(TxBufferFull),
1335
       .almost_full(TxBufferAlmostFull),
1336
       .almost_empty(TxBufferAlmostEmpty),
1337
       .empty(TxBufferEmpty),
1338
       .cnt(txfifo_cnt)
1339
       );
1340 39 mohor
 
1341 354 olof
// Start: Generation of the TxStartFrm_wb which is then synchronized to the
1342
// MTxClk
1343 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1344 38 mohor
begin
1345 40 mohor
  if(Reset)
1346 352 olof
    TxStartFrm_wb <= 1'b0;
1347 38 mohor
  else
1348 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1349 352 olof
    TxStartFrm_wb <= 1'b1;
1350 38 mohor
  else
1351 39 mohor
  if(TxStartFrm_syncb2)
1352 352 olof
    TxStartFrm_wb <= 1'b0;
1353 38 mohor
end
1354
 
1355 354 olof
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's
1356
// blocked.
1357 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1358 38 mohor
begin
1359 40 mohor
  if(Reset)
1360 352 olof
    StartOccured <= 1'b0;
1361 38 mohor
  else
1362 39 mohor
  if(TxStartFrm_wb)
1363 352 olof
    StartOccured <= 1'b1;
1364 38 mohor
  else
1365 39 mohor
  if(ResetTxBDReady)
1366 352 olof
    StartOccured <= 1'b0;
1367 38 mohor
end
1368
 
1369 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1370 40 mohor
always @ (posedge MTxClk or posedge Reset)
1371 39 mohor
begin
1372 40 mohor
  if(Reset)
1373 352 olof
    TxStartFrm_sync1 <= 1'b0;
1374 39 mohor
  else
1375 352 olof
    TxStartFrm_sync1 <= TxStartFrm_wb;
1376 39 mohor
end
1377 38 mohor
 
1378 40 mohor
always @ (posedge MTxClk or posedge Reset)
1379 39 mohor
begin
1380 40 mohor
  if(Reset)
1381 352 olof
    TxStartFrm_sync2 <= 1'b0;
1382 39 mohor
  else
1383 352 olof
    TxStartFrm_sync2 <= TxStartFrm_sync1;
1384 39 mohor
end
1385
 
1386 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1387 38 mohor
begin
1388 40 mohor
  if(Reset)
1389 352 olof
    TxStartFrm_syncb1 <= 1'b0;
1390 38 mohor
  else
1391 352 olof
    TxStartFrm_syncb1 <= TxStartFrm_sync2;
1392 38 mohor
end
1393
 
1394 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1395 38 mohor
begin
1396 40 mohor
  if(Reset)
1397 352 olof
    TxStartFrm_syncb2 <= 1'b0;
1398 38 mohor
  else
1399 352 olof
    TxStartFrm_syncb2 <= TxStartFrm_syncb1;
1400 39 mohor
end
1401
 
1402 40 mohor
always @ (posedge MTxClk or posedge Reset)
1403 39 mohor
begin
1404 40 mohor
  if(Reset)
1405 352 olof
    TxStartFrm <= 1'b0;
1406 38 mohor
  else
1407 39 mohor
  if(TxStartFrm_sync2)
1408 352 olof
    TxStartFrm <= 1'b1;
1409 39 mohor
  else
1410 354 olof
  if(TxUsedData_q | ~TxStartFrm_sync2 &
1411
     (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
1412 352 olof
    TxStartFrm <= 1'b0;
1413 38 mohor
end
1414 354 olof
// End: Generation of the TxStartFrm_wb which is then synchronized to the
1415
// MTxClk
1416 38 mohor
 
1417
 
1418 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1419 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1420 38 mohor
begin
1421 40 mohor
  if(Reset)
1422 352 olof
    TxEndFrm_wb <= 1'b0;
1423 38 mohor
  else
1424 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1425 352 olof
    TxEndFrm_wb <= 1'b1;
1426 38 mohor
  else
1427 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1428 352 olof
    TxEndFrm_wb <= 1'b0;
1429 38 mohor
end
1430
 
1431
// Marks which bytes are valid within the word.
1432 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1433 38 mohor
 
1434
 
1435 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1436 38 mohor
begin
1437 40 mohor
  if(Reset)
1438 352 olof
    LatchValidBytes <= 1'b0;
1439 38 mohor
  else
1440 39 mohor
  if(TxLengthLt4 & TxBDReady)
1441 352 olof
    LatchValidBytes <= 1'b1;
1442 38 mohor
  else
1443 352 olof
    LatchValidBytes <= 1'b0;
1444 38 mohor
end
1445
 
1446 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1447 38 mohor
begin
1448 40 mohor
  if(Reset)
1449 352 olof
    LatchValidBytes_q <= 1'b0;
1450 38 mohor
  else
1451 352 olof
    LatchValidBytes_q <= LatchValidBytes;
1452 38 mohor
end
1453
 
1454
 
1455 39 mohor
// Latching valid bytes
1456 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1457 38 mohor
begin
1458 40 mohor
  if(Reset)
1459 352 olof
    TxValidBytesLatched <= 2'h0;
1460 38 mohor
  else
1461 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1462 352 olof
    TxValidBytesLatched <= TxValidBytes;
1463 39 mohor
  else
1464
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1465 352 olof
    TxValidBytesLatched <= 2'h0;
1466 38 mohor
end
1467
 
1468
 
1469
assign TxIRQEn          = TxStatus[14];
1470 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1471
assign PerPacketPad     = TxStatus[12];
1472
assign PerPacketCrcEn   = TxStatus[11];
1473 38 mohor
 
1474
 
1475 77 mohor
assign RxIRQEn         = RxStatus[14];
1476 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1477 38 mohor
 
1478
 
1479 354 olof
// Temporary Tx and Rx buffer descriptor address
1480
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite  & ~WrapTxStatusBit}} &
1481
                              (TxBDAddress + 1'b1); // Tx BD increment or wrap
1482
                                                    // (last BD)
1483 38 mohor
 
1484 354 olof
assign TempRxBDAddress[7:1] =
1485
  {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
1486
  {7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1); // Using next Rx BD
1487
                                                // (increment address)
1488 38 mohor
 
1489
// Latching Tx buffer descriptor address
1490 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1491 38 mohor
begin
1492 40 mohor
  if(Reset)
1493 352 olof
    TxBDAddress <= 7'h0;
1494 321 igorm
  else if (r_TxEn & (~r_TxEn_q))
1495 352 olof
    TxBDAddress <= 7'h0;
1496 321 igorm
  else if (TxStatusWrite)
1497 352 olof
    TxBDAddress <= TempTxBDAddress;
1498 38 mohor
end
1499
 
1500
// Latching Rx buffer descriptor address
1501 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1502 38 mohor
begin
1503 40 mohor
  if(Reset)
1504 352 olof
    RxBDAddress <= 7'h0;
1505 321 igorm
  else if(r_RxEn & (~r_RxEn_q))
1506 352 olof
    RxBDAddress <= r_TxBDNum[6:0];
1507 321 igorm
  else if(RxStatusWrite)
1508 352 olof
    RxBDAddress <= TempRxBDAddress;
1509 38 mohor
end
1510
 
1511 354 olof
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0],
1512
                                RetryLimit, LateCollLatched, DeferLatched,
1513
                                CarrierSenseLost};
1514 38 mohor
 
1515 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1516 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1517 38 mohor
 
1518 60 mohor
 
1519 38 mohor
// Signals used for various purposes
1520 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1521 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1522
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1523
 
1524
 
1525 39 mohor
// Generating delayed signals
1526 40 mohor
always @ (posedge MTxClk or posedge Reset)
1527 38 mohor
begin
1528 40 mohor
  if(Reset)
1529 39 mohor
    begin
1530 352 olof
      TxAbort_q      <= 1'b0;
1531
      TxRetry_q      <= 1'b0;
1532
      TxUsedData_q   <= 1'b0;
1533 39 mohor
    end
1534 38 mohor
  else
1535 39 mohor
    begin
1536 352 olof
      TxAbort_q      <= TxAbort;
1537
      TxRetry_q      <= TxRetry;
1538
      TxUsedData_q   <= TxUsedData;
1539 39 mohor
    end
1540 38 mohor
end
1541
 
1542
// Generating delayed signals
1543 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1544 38 mohor
begin
1545 40 mohor
  if(Reset)
1546 38 mohor
    begin
1547 352 olof
      TxDone_wb_q   <= 1'b0;
1548
      TxAbort_wb_q  <= 1'b0;
1549
      TxRetry_wb_q  <= 1'b0;
1550 38 mohor
    end
1551
  else
1552
    begin
1553 352 olof
      TxDone_wb_q   <= TxDone_wb;
1554
      TxAbort_wb_q  <= TxAbort_wb;
1555
      TxRetry_wb_q  <= TxRetry_wb;
1556 38 mohor
    end
1557
end
1558
 
1559
 
1560 219 mohor
reg TxAbortPacketBlocked;
1561
always @ (posedge WB_CLK_I or posedge Reset)
1562
begin
1563
  if(Reset)
1564 352 olof
    TxAbortPacket <= 1'b0;
1565 219 mohor
  else
1566 354 olof
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
1567
    (~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
1568
    (~TxAbortPacketBlocked))
1569 352 olof
    TxAbortPacket <= 1'b1;
1570 219 mohor
  else
1571 352 olof
    TxAbortPacket <= 1'b0;
1572 219 mohor
end
1573
 
1574
 
1575
always @ (posedge WB_CLK_I or posedge Reset)
1576
begin
1577
  if(Reset)
1578 352 olof
    TxAbortPacket_NotCleared <= 1'b0;
1579 221 mohor
  else
1580 272 tadejm
  if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
1581 352 olof
    TxAbortPacket_NotCleared <= 1'b0;
1582 272 tadejm
  else
1583 354 olof
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
1584
     (~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
1585
     (~TxAbortPacketBlocked))
1586 352 olof
    TxAbortPacket_NotCleared <= 1'b1;
1587 221 mohor
end
1588
 
1589
 
1590
always @ (posedge WB_CLK_I or posedge Reset)
1591
begin
1592
  if(Reset)
1593 352 olof
    TxAbortPacketBlocked <= 1'b0;
1594 219 mohor
  else
1595 280 mohor
  if(!TxAbort_wb & TxAbort_wb_q)
1596 352 olof
    TxAbortPacketBlocked <= 1'b0;
1597 280 mohor
  else
1598 219 mohor
  if(TxAbortPacket)
1599 352 olof
    TxAbortPacketBlocked <= 1'b1;
1600 219 mohor
end
1601
 
1602
 
1603
reg TxRetryPacketBlocked;
1604
always @ (posedge WB_CLK_I or posedge Reset)
1605
begin
1606
  if(Reset)
1607 352 olof
    TxRetryPacket <= 1'b0;
1608 219 mohor
  else
1609 354 olof
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1610
     !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1611 352 olof
    TxRetryPacket <= 1'b1;
1612 219 mohor
  else
1613 352 olof
    TxRetryPacket <= 1'b0;
1614 219 mohor
end
1615
 
1616
 
1617
always @ (posedge WB_CLK_I or posedge Reset)
1618
begin
1619
  if(Reset)
1620 352 olof
    TxRetryPacket_NotCleared <= 1'b0;
1621 221 mohor
  else
1622 272 tadejm
  if(StartTxBDRead)
1623 352 olof
    TxRetryPacket_NotCleared <= 1'b0;
1624 272 tadejm
  else
1625 354 olof
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1626
     !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1627 352 olof
    TxRetryPacket_NotCleared <= 1'b1;
1628 221 mohor
end
1629
 
1630
 
1631
always @ (posedge WB_CLK_I or posedge Reset)
1632
begin
1633
  if(Reset)
1634 352 olof
    TxRetryPacketBlocked <= 1'b0;
1635 219 mohor
  else
1636 280 mohor
  if(!TxRetry_wb & TxRetry_wb_q)
1637 352 olof
    TxRetryPacketBlocked <= 1'b0;
1638 280 mohor
  else
1639 219 mohor
  if(TxRetryPacket)
1640 352 olof
    TxRetryPacketBlocked <= 1'b1;
1641 219 mohor
end
1642
 
1643
 
1644 221 mohor
reg TxDonePacketBlocked;
1645
always @ (posedge WB_CLK_I or posedge Reset)
1646
begin
1647
  if(Reset)
1648 352 olof
    TxDonePacket <= 1'b0;
1649 221 mohor
  else
1650 354 olof
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1651
     !TxDonePacketBlocked | TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1652 352 olof
    TxDonePacket <= 1'b1;
1653 221 mohor
  else
1654 352 olof
    TxDonePacket <= 1'b0;
1655 221 mohor
end
1656
 
1657
 
1658
always @ (posedge WB_CLK_I or posedge Reset)
1659
begin
1660
  if(Reset)
1661 352 olof
    TxDonePacket_NotCleared <= 1'b0;
1662 221 mohor
  else
1663 272 tadejm
  if(TxEn & TxEn_q & TxDonePacket_NotCleared)
1664 352 olof
    TxDonePacket_NotCleared <= 1'b0;
1665 272 tadejm
  else
1666 354 olof
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1667
     (~TxDonePacketBlocked) | TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
1668 352 olof
    TxDonePacket_NotCleared <= 1'b1;
1669 221 mohor
end
1670
 
1671
 
1672
always @ (posedge WB_CLK_I or posedge Reset)
1673
begin
1674
  if(Reset)
1675 352 olof
    TxDonePacketBlocked <= 1'b0;
1676 221 mohor
  else
1677 280 mohor
  if(!TxDone_wb & TxDone_wb_q)
1678 352 olof
    TxDonePacketBlocked <= 1'b0;
1679 280 mohor
  else
1680 221 mohor
  if(TxDonePacket)
1681 352 olof
    TxDonePacketBlocked <= 1'b1;
1682 221 mohor
end
1683
 
1684
 
1685 38 mohor
// Indication of the last word
1686 40 mohor
always @ (posedge MTxClk or posedge Reset)
1687 38 mohor
begin
1688 40 mohor
  if(Reset)
1689 352 olof
    LastWord <= 1'b0;
1690 38 mohor
  else
1691
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1692 352 olof
    LastWord <= 1'b0;
1693 38 mohor
  else
1694
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1695 352 olof
    LastWord <= TxEndFrm_wb;
1696 38 mohor
end
1697
 
1698
 
1699
// Tx end frame generation
1700 40 mohor
always @ (posedge MTxClk or posedge Reset)
1701 38 mohor
begin
1702 40 mohor
  if(Reset)
1703 352 olof
    TxEndFrm <= 1'b0;
1704 38 mohor
  else
1705 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1706 352 olof
    TxEndFrm <= 1'b0;
1707 38 mohor
  else
1708
  if(Flop & LastWord)
1709
    begin
1710 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1711 352 olof
        1 : TxEndFrm <= TxByteCnt == 2'h0;
1712
        2 : TxEndFrm <= TxByteCnt == 2'h1;
1713
        3 : TxEndFrm <= TxByteCnt == 2'h2;
1714
 
1715
        default : TxEndFrm <= 1'b0;
1716 38 mohor
      endcase
1717
    end
1718
end
1719
 
1720
 
1721
// Tx data selection (latching)
1722 40 mohor
always @ (posedge MTxClk or posedge Reset)
1723 38 mohor
begin
1724 40 mohor
  if(Reset)
1725 352 olof
    TxData <= 0;
1726 38 mohor
  else
1727 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1728 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1729 354 olof
      2'h0 : TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
1730
      2'h1 : TxData <= TxData_wb[23:16];// Big Endian Byte Ordering
1731
      2'h2 : TxData <= TxData_wb[15:08];// Big Endian Byte Ordering
1732
      2'h3 : TxData <= TxData_wb[07:00];// Big Endian Byte Ordering
1733 96 mohor
    endcase
1734 38 mohor
  else
1735 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1736 354 olof
    TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
1737 96 mohor
  else
1738 38 mohor
  if(TxUsedData & Flop)
1739
    begin
1740 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1741 354 olof
 
1742 352 olof
        1 : TxData <= TxDataLatched[23:16];
1743
        2 : TxData <= TxDataLatched[15:8];
1744
        3 : TxData <= TxDataLatched[7:0];
1745 38 mohor
      endcase
1746
    end
1747
end
1748
 
1749
 
1750
// Latching tx data
1751 40 mohor
always @ (posedge MTxClk or posedge Reset)
1752 38 mohor
begin
1753 40 mohor
  if(Reset)
1754 352 olof
    TxDataLatched[31:0] <= 32'h0;
1755 38 mohor
  else
1756 354 olof
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 |
1757
     TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1758 352 olof
    TxDataLatched[31:0] <= TxData_wb[31:0];
1759 38 mohor
end
1760
 
1761
 
1762
// Tx under run
1763 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1764 38 mohor
begin
1765 40 mohor
  if(Reset)
1766 352 olof
    TxUnderRun_wb <= 1'b0;
1767 38 mohor
  else
1768 39 mohor
  if(TxAbortPulse)
1769 352 olof
    TxUnderRun_wb <= 1'b0;
1770 60 mohor
  else
1771
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1772 352 olof
    TxUnderRun_wb <= 1'b1;
1773 60 mohor
end
1774
 
1775
 
1776 159 mohor
reg TxUnderRun_sync1;
1777
 
1778 60 mohor
// Tx under run
1779
always @ (posedge MTxClk or posedge Reset)
1780
begin
1781
  if(Reset)
1782 352 olof
    TxUnderRun_sync1 <= 1'b0;
1783 38 mohor
  else
1784 60 mohor
  if(TxUnderRun_wb)
1785 352 olof
    TxUnderRun_sync1 <= 1'b1;
1786 60 mohor
  else
1787 159 mohor
  if(BlockingTxStatusWrite_sync2)
1788 352 olof
    TxUnderRun_sync1 <= 1'b0;
1789 159 mohor
end
1790
 
1791
// Tx under run
1792
always @ (posedge MTxClk or posedge Reset)
1793
begin
1794
  if(Reset)
1795 352 olof
    TxUnderRun <= 1'b0;
1796 159 mohor
  else
1797
  if(BlockingTxStatusWrite_sync2)
1798 352 olof
    TxUnderRun <= 1'b0;
1799 159 mohor
  else
1800
  if(TxUnderRun_sync1)
1801 352 olof
    TxUnderRun <= 1'b1;
1802 38 mohor
end
1803
 
1804
 
1805
// Tx Byte counter
1806 40 mohor
always @ (posedge MTxClk or posedge Reset)
1807 38 mohor
begin
1808 40 mohor
  if(Reset)
1809 352 olof
    TxByteCnt <= 2'h0;
1810 38 mohor
  else
1811
  if(TxAbort_q | TxRetry_q)
1812 352 olof
    TxByteCnt <= 2'h0;
1813 38 mohor
  else
1814
  if(TxStartFrm & ~TxUsedData)
1815 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1816 352 olof
      2'h0 : TxByteCnt <= 2'h1;
1817
      2'h1 : TxByteCnt <= 2'h2;
1818
      2'h2 : TxByteCnt <= 2'h3;
1819
      2'h3 : TxByteCnt <= 2'h0;
1820 96 mohor
    endcase
1821 38 mohor
  else
1822
  if(TxUsedData & Flop)
1823 352 olof
    TxByteCnt <= TxByteCnt + 1'b1;
1824 38 mohor
end
1825
 
1826 39 mohor
 
1827 150 mohor
always @ (posedge MTxClk or posedge Reset)
1828
begin
1829
  if(Reset)
1830 352 olof
    ReadTxDataFromFifo_tck <= 1'b0;
1831 150 mohor
  else
1832 354 olof
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 &
1833
     ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1834 352 olof
     ReadTxDataFromFifo_tck <= 1'b1;
1835 150 mohor
  else
1836
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1837 352 olof
    ReadTxDataFromFifo_tck <= 1'b0;
1838 38 mohor
end
1839
 
1840 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1841 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1842 38 mohor
begin
1843 40 mohor
  if(Reset)
1844 352 olof
    ReadTxDataFromFifo_sync1 <= 1'b0;
1845 38 mohor
  else
1846 352 olof
    ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck;
1847 39 mohor
end
1848 38 mohor
 
1849 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1850 38 mohor
begin
1851 40 mohor
  if(Reset)
1852 352 olof
    ReadTxDataFromFifo_sync2 <= 1'b0;
1853 38 mohor
  else
1854 352 olof
    ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1;
1855 38 mohor
end
1856
 
1857 40 mohor
always @ (posedge MTxClk or posedge Reset)
1858 38 mohor
begin
1859 40 mohor
  if(Reset)
1860 352 olof
    ReadTxDataFromFifo_syncb1 <= 1'b0;
1861 38 mohor
  else
1862 352 olof
    ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2;
1863 38 mohor
end
1864
 
1865 40 mohor
always @ (posedge MTxClk or posedge Reset)
1866 38 mohor
begin
1867 40 mohor
  if(Reset)
1868 352 olof
    ReadTxDataFromFifo_syncb2 <= 1'b0;
1869 38 mohor
  else
1870 352 olof
    ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1;
1871 38 mohor
end
1872
 
1873 150 mohor
always @ (posedge MTxClk or posedge Reset)
1874
begin
1875
  if(Reset)
1876 352 olof
    ReadTxDataFromFifo_syncb3 <= 1'b0;
1877 150 mohor
  else
1878 352 olof
    ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2;
1879 150 mohor
end
1880
 
1881 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1882 38 mohor
begin
1883 40 mohor
  if(Reset)
1884 352 olof
    ReadTxDataFromFifo_sync3 <= 1'b0;
1885 38 mohor
  else
1886 352 olof
    ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2;
1887 38 mohor
end
1888
 
1889 354 olof
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 &
1890
                               ~ReadTxDataFromFifo_sync3;
1891
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization
1892
// to the WB_CLK_I
1893 38 mohor
 
1894
 
1895 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1896 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1897 38 mohor
begin
1898 40 mohor
  if(Reset)
1899 352 olof
    TxRetrySync1 <= 1'b0;
1900 38 mohor
  else
1901 352 olof
    TxRetrySync1 <= TxRetry;
1902 38 mohor
end
1903
 
1904 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1905 38 mohor
begin
1906 40 mohor
  if(Reset)
1907 352 olof
    TxRetry_wb <= 1'b0;
1908 38 mohor
  else
1909 352 olof
    TxRetry_wb <= TxRetrySync1;
1910 38 mohor
end
1911
 
1912
 
1913 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1914 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1915 38 mohor
begin
1916 40 mohor
  if(Reset)
1917 352 olof
    TxDoneSync1 <= 1'b0;
1918 38 mohor
  else
1919 352 olof
    TxDoneSync1 <= TxDone;
1920 38 mohor
end
1921
 
1922 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1923 38 mohor
begin
1924 40 mohor
  if(Reset)
1925 352 olof
    TxDone_wb <= 1'b0;
1926 38 mohor
  else
1927 352 olof
    TxDone_wb <= TxDoneSync1;
1928 38 mohor
end
1929
 
1930 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1931 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1932 38 mohor
begin
1933 40 mohor
  if(Reset)
1934 352 olof
    TxAbortSync1 <= 1'b0;
1935 38 mohor
  else
1936 352 olof
    TxAbortSync1 <= TxAbort;
1937 38 mohor
end
1938
 
1939 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1940 38 mohor
begin
1941 40 mohor
  if(Reset)
1942 352 olof
    TxAbort_wb <= 1'b0;
1943 38 mohor
  else
1944 352 olof
    TxAbort_wb <= TxAbortSync1;
1945 38 mohor
end
1946
 
1947
 
1948 354 olof
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 |
1949
                       r_RxEn & ~r_RxEn_q;
1950 39 mohor
 
1951 40 mohor
// Reading the Rx buffer descriptor
1952
always @ (posedge WB_CLK_I or posedge Reset)
1953
begin
1954
  if(Reset)
1955 352 olof
    RxBDRead <= 1'b0;
1956 40 mohor
  else
1957 166 mohor
  if(StartRxBDRead & ~RxReady)
1958 352 olof
    RxBDRead <= 1'b1;
1959 40 mohor
  else
1960
  if(RxBDReady)
1961 352 olof
    RxBDRead <= 1'b0;
1962 40 mohor
end
1963 39 mohor
 
1964
 
1965 354 olof
// Reading of the next receive buffer descriptor starts after reception status
1966
// is written to the previous one.
1967 38 mohor
 
1968
// Latching READY status of the Rx buffer descriptor
1969 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1970 38 mohor
begin
1971 40 mohor
  if(Reset)
1972 352 olof
    RxBDReady <= 1'b0;
1973 38 mohor
  else
1974 166 mohor
  if(RxPointerRead)
1975 352 olof
    RxBDReady <= 1'b0;
1976 150 mohor
  else
1977 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1978 354 olof
    RxBDReady <= ram_do[15];// RxBDReady is sampled only once at the beginning
1979 38 mohor
end
1980
 
1981 40 mohor
// Latching Rx buffer descriptor status
1982 354 olof
// Data is avaliable one cycle after the access is started (at that time
1983
// signal RxEn is not active)
1984 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1985 38 mohor
begin
1986 40 mohor
  if(Reset)
1987 352 olof
    RxStatus <= 2'h0;
1988 38 mohor
  else
1989 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1990 352 olof
    RxStatus <= ram_do[14:13];
1991 38 mohor
end
1992
 
1993
 
1994 166 mohor
// RxReady generation
1995
always @ (posedge WB_CLK_I or posedge Reset)
1996
begin
1997
  if(Reset)
1998 352 olof
    RxReady <= 1'b0;
1999 354 olof
  else if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
2000 352 olof
    RxReady <= 1'b0;
2001 354 olof
  else if(RxEn & RxEn_q & RxPointerRead)
2002 352 olof
    RxReady <= 1'b1;
2003 166 mohor
end
2004 38 mohor
 
2005
 
2006 40 mohor
// Reading Rx BD pointer
2007
assign StartRxPointerRead = RxBDRead & RxBDReady;
2008
 
2009
// Reading Tx BD Pointer
2010
always @ (posedge WB_CLK_I or posedge Reset)
2011 38 mohor
begin
2012 40 mohor
  if(Reset)
2013 352 olof
    RxPointerRead <= 1'b0;
2014 38 mohor
  else
2015 40 mohor
  if(StartRxPointerRead)
2016 352 olof
    RxPointerRead <= 1'b1;
2017 38 mohor
  else
2018 166 mohor
  if(RxEn & RxEn_q)
2019 352 olof
    RxPointerRead <= 1'b0;
2020 38 mohor
end
2021
 
2022 113 mohor
 
2023 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
2024
always @ (posedge WB_CLK_I or posedge Reset)
2025
begin
2026
  if(Reset)
2027 352 olof
    RxPointerMSB <= 30'h0;
2028 40 mohor
  else
2029
  if(RxEn & RxEn_q & RxPointerRead)
2030 352 olof
    RxPointerMSB <= ram_do[31:2];
2031 40 mohor
  else
2032 113 mohor
  if(MasterWbRX & m_wb_ack_i)
2033 354 olof
      RxPointerMSB <= RxPointerMSB + 1'b1; // Word access (always word access.
2034
                                           // m_wb_sel_o are used for
2035
                                           // selecting bytes)
2036 40 mohor
end
2037 38 mohor
 
2038
 
2039 354 olof
//Latching last addresses from buffer descriptor (used as byte-half-word
2040
//indicator);
2041 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2042
begin
2043
  if(Reset)
2044 352 olof
    RxPointerLSB_rst[1:0] <= 0;
2045 96 mohor
  else
2046 354 olof
  if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
2047 352 olof
    RxPointerLSB_rst[1:0] <= 0;
2048 96 mohor
  else
2049
  if(RxEn & RxEn_q & RxPointerRead)
2050 352 olof
    RxPointerLSB_rst[1:0] <= ram_do[1:0];
2051 96 mohor
end
2052
 
2053
 
2054 159 mohor
always @ (RxPointerLSB_rst)
2055 96 mohor
begin
2056 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
2057
    2'h0 : RxByteSel[3:0] = 4'hf;
2058
    2'h1 : RxByteSel[3:0] = 4'h7;
2059
    2'h2 : RxByteSel[3:0] = 4'h3;
2060
    2'h3 : RxByteSel[3:0] = 4'h1;
2061 96 mohor
  endcase
2062
end
2063
 
2064
 
2065
always @ (posedge WB_CLK_I or posedge Reset)
2066
begin
2067
  if(Reset)
2068 352 olof
    RxEn_needed <= 1'b0;
2069 354 olof
  else if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
2070 352 olof
    RxEn_needed <= 1'b1;
2071 354 olof
  else if(RxPointerRead & RxEn & RxEn_q)
2072 352 olof
    RxEn_needed <= 1'b0;
2073 38 mohor
end
2074
 
2075
 
2076 354 olof
// Reception status is written back to the buffer descriptor after the end
2077
// of frame is detected.
2078 40 mohor
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
2079 38 mohor
 
2080
 
2081
// Indicating that last byte is being reveived
2082 40 mohor
always @ (posedge MRxClk or posedge Reset)
2083 38 mohor
begin
2084 40 mohor
  if(Reset)
2085 352 olof
    LastByteIn <= 1'b0;
2086 38 mohor
  else
2087 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
2088 352 olof
    LastByteIn <= 1'b0;
2089 38 mohor
  else
2090 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
2091 352 olof
    LastByteIn <= 1'b1;
2092 38 mohor
end
2093
 
2094 354 olof
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) &
2095
                           RxEnableWindow;
2096 118 mohor
 
2097 38 mohor
// Indicating that data reception will end
2098 40 mohor
always @ (posedge MRxClk or posedge Reset)
2099 38 mohor
begin
2100 40 mohor
  if(Reset)
2101 352 olof
    ShiftWillEnd <= 1'b0;
2102 38 mohor
  else
2103 159 mohor
  if(ShiftEnded_rck | RxAbort)
2104 352 olof
    ShiftWillEnd <= 1'b0;
2105 38 mohor
  else
2106 40 mohor
  if(StartShiftWillEnd)
2107 352 olof
    ShiftWillEnd <= 1'b1;
2108 38 mohor
end
2109
 
2110
 
2111
// Receive byte counter
2112 40 mohor
always @ (posedge MRxClk or posedge Reset)
2113 38 mohor
begin
2114 40 mohor
  if(Reset)
2115 352 olof
    RxByteCnt <= 2'h0;
2116 38 mohor
  else
2117 159 mohor
  if(ShiftEnded_rck | RxAbort)
2118 352 olof
    RxByteCnt <= 2'h0;
2119 97 lampret
  else
2120 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2121 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2122 352 olof
      2'h0 : RxByteCnt <= 2'h1;
2123
      2'h1 : RxByteCnt <= 2'h2;
2124
      2'h2 : RxByteCnt <= 2'h3;
2125
      2'h3 : RxByteCnt <= 2'h0;
2126 96 mohor
    endcase
2127 38 mohor
  else
2128 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2129 352 olof
    RxByteCnt <= RxByteCnt + 1'b1;
2130 38 mohor
end
2131
 
2132
 
2133
// Indicates how many bytes are valid within the last word
2134 40 mohor
always @ (posedge MRxClk or posedge Reset)
2135 38 mohor
begin
2136 40 mohor
  if(Reset)
2137 352 olof
    RxValidBytes <= 2'h1;
2138 38 mohor
  else
2139 96 mohor
  if(RxValid & RxStartFrm)
2140 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2141 352 olof
      2'h0 : RxValidBytes <= 2'h1;
2142
      2'h1 : RxValidBytes <= 2'h2;
2143
      2'h2 : RxValidBytes <= 2'h3;
2144
      2'h3 : RxValidBytes <= 2'h0;
2145 96 mohor
    endcase
2146 38 mohor
  else
2147 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2148 352 olof
    RxValidBytes <= RxValidBytes + 1'b1;
2149 38 mohor
end
2150
 
2151
 
2152 40 mohor
always @ (posedge MRxClk or posedge Reset)
2153 38 mohor
begin
2154 40 mohor
  if(Reset)
2155 352 olof
    RxDataLatched1       <= 24'h0;
2156 38 mohor
  else
2157 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2158 96 mohor
    if(RxStartFrm)
2159 40 mohor
    begin
2160 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2161 354 olof
        // Big Endian Byte Ordering
2162
        2'h0:        RxDataLatched1[31:24] <= RxData;
2163 352 olof
        2'h1:        RxDataLatched1[23:16] <= RxData;
2164
        2'h2:        RxDataLatched1[15:8]  <= RxData;
2165
        2'h3:        RxDataLatched1        <= RxDataLatched1;
2166 96 mohor
      endcase
2167
    end
2168
    else if (RxEnableWindow)
2169
    begin
2170 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2171 354 olof
        // Big Endian Byte Ordering
2172
        2'h0:        RxDataLatched1[31:24] <= RxData;
2173 352 olof
        2'h1:        RxDataLatched1[23:16] <= RxData;
2174
        2'h2:        RxDataLatched1[15:8]  <= RxData;
2175
        2'h3:        RxDataLatched1        <= RxDataLatched1;
2176 40 mohor
      endcase
2177
    end
2178 38 mohor
end
2179
 
2180 40 mohor
// Assembling data that will be written to the rx_fifo
2181
always @ (posedge MRxClk or posedge Reset)
2182 38 mohor
begin
2183 40 mohor
  if(Reset)
2184 352 olof
    RxDataLatched2 <= 32'h0;
2185 38 mohor
  else
2186 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2187 354 olof
    // Big Endian Byte Ordering
2188
    RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
2189 38 mohor
  else
2190 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2191 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2192 354 olof
      // Big Endian Byte Ordering
2193
 
2194 352 olof
      1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0};
2195
      2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0};
2196
      3 : RxDataLatched2 <= {RxDataLatched1[31:8],   8'h0};
2197 40 mohor
    endcase
2198 38 mohor
end
2199
 
2200
 
2201 40 mohor
// Indicating start of the reception process
2202 354 olof
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm &
2203
                              RxEnableWindow & (&RxByteCnt))
2204
                              |(RxValid & RxReady &  RxStartFrm &
2205
                              (&RxPointerLSB_rst))
2206
                              |(ShiftWillEnd & LastByteIn & (&RxByteCnt));
2207 38 mohor
 
2208 150 mohor
always @ (posedge MRxClk or posedge Reset)
2209
begin
2210
  if(Reset)
2211 352 olof
    WriteRxDataToFifo <= 1'b0;
2212 150 mohor
  else
2213
  if(SetWriteRxDataToFifo & ~RxAbort)
2214 352 olof
    WriteRxDataToFifo <= 1'b1;
2215 150 mohor
  else
2216
  if(WriteRxDataToFifoSync2 | RxAbort)
2217 352 olof
    WriteRxDataToFifo <= 1'b0;
2218 150 mohor
end
2219 40 mohor
 
2220 150 mohor
 
2221
always @ (posedge WB_CLK_I or posedge Reset)
2222
begin
2223
  if(Reset)
2224 352 olof
    WriteRxDataToFifoSync1 <= 1'b0;
2225 150 mohor
  else
2226
  if(WriteRxDataToFifo)
2227 352 olof
    WriteRxDataToFifoSync1 <= 1'b1;
2228 150 mohor
  else
2229 352 olof
    WriteRxDataToFifoSync1 <= 1'b0;
2230 150 mohor
end
2231
 
2232
always @ (posedge WB_CLK_I or posedge Reset)
2233
begin
2234
  if(Reset)
2235 352 olof
    WriteRxDataToFifoSync2 <= 1'b0;
2236 150 mohor
  else
2237 352 olof
    WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1;
2238 150 mohor
end
2239
 
2240
always @ (posedge WB_CLK_I or posedge Reset)
2241
begin
2242
  if(Reset)
2243 352 olof
    WriteRxDataToFifoSync3 <= 1'b0;
2244 150 mohor
  else
2245 352 olof
    WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
2246 150 mohor
end
2247
 
2248
 
2249 354 olof
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 &
2250
                              ~WriteRxDataToFifoSync3;
2251 150 mohor
 
2252 40 mohor
 
2253 90 mohor
always @ (posedge MRxClk or posedge Reset)
2254
begin
2255
  if(Reset)
2256 352 olof
    LatchedRxStartFrm <= 0;
2257 90 mohor
  else
2258 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2259 352 olof
    LatchedRxStartFrm <= 1;
2260 90 mohor
  else
2261 150 mohor
  if(SyncRxStartFrm_q)
2262 352 olof
    LatchedRxStartFrm <= 0;
2263 90 mohor
end
2264
 
2265
 
2266
always @ (posedge WB_CLK_I or posedge Reset)
2267
begin
2268
  if(Reset)
2269 352 olof
    SyncRxStartFrm <= 0;
2270 90 mohor
  else
2271
  if(LatchedRxStartFrm)
2272 352 olof
    SyncRxStartFrm <= 1;
2273 90 mohor
  else
2274 352 olof
    SyncRxStartFrm <= 0;
2275 90 mohor
end
2276
 
2277
 
2278
always @ (posedge WB_CLK_I or posedge Reset)
2279
begin
2280
  if(Reset)
2281 352 olof
    SyncRxStartFrm_q <= 0;
2282 90 mohor
  else
2283 352 olof
    SyncRxStartFrm_q <= SyncRxStartFrm;
2284 90 mohor
end
2285
 
2286 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2287
begin
2288
  if(Reset)
2289 352 olof
    SyncRxStartFrm_q2 <= 0;
2290 150 mohor
  else
2291 352 olof
    SyncRxStartFrm_q2 <= SyncRxStartFrm_q;
2292 150 mohor
end
2293 90 mohor
 
2294
 
2295 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2296 90 mohor
 
2297 354 olof
eth_fifo #(
2298
           .DATA_WIDTH(RX_FIFO_DATA_WIDTH),
2299
           .DEPTH(RX_FIFO_DEPTH),
2300
           .CNT_WIDTH(RX_FIFO_CNT_WIDTH))
2301
rx_fifo (
2302
         .clk            (WB_CLK_I),
2303
         .reset          (Reset),
2304
         // Inputs
2305
         .data_in        (RxDataLatched2),
2306
         .write          (WriteRxDataToFifo_wb & ~RxBufferFull),
2307
         .read           (MasterWbRX & m_wb_ack_i),
2308
         .clear          (RxFifoReset),
2309
         // Outputs
2310
         .data_out       (m_wb_dat_o),
2311
         .full           (RxBufferFull),
2312
         .almost_full    (),
2313
         .almost_empty   (RxBufferAlmostEmpty),
2314
         .empty          (RxBufferEmpty),
2315
         .cnt            (rxfifo_cnt)
2316 88 mohor
        );
2317 40 mohor
 
2318 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2319
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2320 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2321 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2322 40 mohor
 
2323
 
2324
// Generation of the end-of-frame signal
2325
always @ (posedge MRxClk or posedge Reset)
2326 38 mohor
begin
2327 40 mohor
  if(Reset)
2328 352 olof
    ShiftEnded_rck <= 1'b0;
2329 38 mohor
  else
2330 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2331 352 olof
    ShiftEnded_rck <= 1'b1;
2332 38 mohor
  else
2333 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2334 352 olof
    ShiftEnded_rck <= 1'b0;
2335 38 mohor
end
2336
 
2337 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2338
begin
2339
  if(Reset)
2340 352 olof
    ShiftEndedSync1 <= 1'b0;
2341 40 mohor
  else
2342 352 olof
    ShiftEndedSync1 <= ShiftEnded_rck;
2343 40 mohor
end
2344 38 mohor
 
2345 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2346 38 mohor
begin
2347 40 mohor
  if(Reset)
2348 352 olof
    ShiftEndedSync2 <= 1'b0;
2349 38 mohor
  else
2350 352 olof
    ShiftEndedSync2 <= ShiftEndedSync1;
2351 40 mohor
end
2352 38 mohor
 
2353 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2354
begin
2355
  if(Reset)
2356 352 olof
    ShiftEndedSync3 <= 1'b0;
2357 118 mohor
  else
2358
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2359 352 olof
    ShiftEndedSync3 <= 1'b1;
2360 118 mohor
  else
2361
  if(ShiftEnded)
2362 352 olof
    ShiftEndedSync3 <= 1'b0;
2363 118 mohor
end
2364 38 mohor
 
2365 40 mohor
// Generation of the end-of-frame signal
2366
always @ (posedge WB_CLK_I or posedge Reset)
2367 38 mohor
begin
2368 40 mohor
  if(Reset)
2369 352 olof
    ShiftEnded <= 1'b0;
2370 38 mohor
  else
2371 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2372 352 olof
    ShiftEnded <= 1'b1;
2373 38 mohor
  else
2374 40 mohor
  if(RxStatusWrite)
2375 352 olof
    ShiftEnded <= 1'b0;
2376 38 mohor
end
2377
 
2378 118 mohor
always @ (posedge MRxClk or posedge Reset)
2379
begin
2380
  if(Reset)
2381 352 olof
    ShiftEndedSync_c1 <= 1'b0;
2382 118 mohor
  else
2383 352 olof
    ShiftEndedSync_c1 <= ShiftEndedSync2;
2384 118 mohor
end
2385 38 mohor
 
2386 118 mohor
always @ (posedge MRxClk or posedge Reset)
2387
begin
2388
  if(Reset)
2389 352 olof
    ShiftEndedSync_c2 <= 1'b0;
2390 118 mohor
  else
2391 352 olof
    ShiftEndedSync_c2 <= ShiftEndedSync_c1;
2392 118 mohor
end
2393
 
2394 40 mohor
// Generation of the end-of-frame signal
2395
always @ (posedge MRxClk or posedge Reset)
2396 38 mohor
begin
2397 40 mohor
  if(Reset)
2398 352 olof
    RxEnableWindow <= 1'b0;
2399 354 olof
  else if(RxStartFrm)
2400 352 olof
    RxEnableWindow <= 1'b1;
2401 354 olof
  else if(RxEndFrm | RxAbort)
2402 352 olof
    RxEnableWindow <= 1'b0;
2403 38 mohor
end
2404
 
2405
 
2406 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2407 38 mohor
begin
2408 40 mohor
  if(Reset)
2409 352 olof
    RxAbortSync1 <= 1'b0;
2410 38 mohor
  else
2411 352 olof
    RxAbortSync1 <= RxAbortLatched;
2412 40 mohor
end
2413
 
2414
always @ (posedge WB_CLK_I or posedge Reset)
2415
begin
2416
  if(Reset)
2417 352 olof
    RxAbortSync2 <= 1'b0;
2418 38 mohor
  else
2419 352 olof
    RxAbortSync2 <= RxAbortSync1;
2420 38 mohor
end
2421
 
2422 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2423
begin
2424
  if(Reset)
2425 352 olof
    RxAbortSync3 <= 1'b0;
2426 150 mohor
  else
2427 352 olof
    RxAbortSync3 <= RxAbortSync2;
2428 150 mohor
end
2429
 
2430
always @ (posedge WB_CLK_I or posedge Reset)
2431
begin
2432
  if(Reset)
2433 352 olof
    RxAbortSync4 <= 1'b0;
2434 150 mohor
  else
2435 352 olof
    RxAbortSync4 <= RxAbortSync3;
2436 150 mohor
end
2437
 
2438 40 mohor
always @ (posedge MRxClk or posedge Reset)
2439
begin
2440
  if(Reset)
2441 352 olof
    RxAbortSyncb1 <= 1'b0;
2442 40 mohor
  else
2443 352 olof
    RxAbortSyncb1 <= RxAbortSync2;
2444 40 mohor
end
2445 38 mohor
 
2446 40 mohor
always @ (posedge MRxClk or posedge Reset)
2447 38 mohor
begin
2448 40 mohor
  if(Reset)
2449 352 olof
    RxAbortSyncb2 <= 1'b0;
2450 38 mohor
  else
2451 352 olof
    RxAbortSyncb2 <= RxAbortSyncb1;
2452 38 mohor
end
2453
 
2454
 
2455 64 mohor
always @ (posedge MRxClk or posedge Reset)
2456
begin
2457
  if(Reset)
2458 352 olof
    RxAbortLatched <= 1'b0;
2459 64 mohor
  else
2460 150 mohor
  if(RxAbortSyncb2)
2461 352 olof
    RxAbortLatched <= 1'b0;
2462 150 mohor
  else
2463 64 mohor
  if(RxAbort)
2464 352 olof
    RxAbortLatched <= 1'b1;
2465 64 mohor
end
2466 40 mohor
 
2467 64 mohor
 
2468 42 mohor
always @ (posedge MRxClk or posedge Reset)
2469
begin
2470
  if(Reset)
2471 352 olof
    LatchedRxLength[15:0] <= 16'h0;
2472 42 mohor
  else
2473 150 mohor
  if(LoadRxStatus)
2474 352 olof
    LatchedRxLength[15:0] <= RxLength[15:0];
2475 42 mohor
end
2476
 
2477
 
2478 354 olof
assign RxStatusIn = {ReceivedPauseFrm,
2479
                     AddressMiss,
2480
                     RxOverrun,
2481
                     InvalidSymbol,
2482
                     DribbleNibble,
2483
                     ReceivedPacketTooBig,
2484
                     ShortFrame,
2485
                     LatchedCrcError,
2486
                     RxLateCollision};
2487 42 mohor
 
2488
always @ (posedge MRxClk or posedge Reset)
2489
begin
2490
  if(Reset)
2491 352 olof
    RxStatusInLatched <= 'h0;
2492 42 mohor
  else
2493 150 mohor
  if(LoadRxStatus)
2494 352 olof
    RxStatusInLatched <= RxStatusIn;
2495 42 mohor
end
2496
 
2497
 
2498 60 mohor
// Rx overrun
2499
always @ (posedge WB_CLK_I or posedge Reset)
2500
begin
2501
  if(Reset)
2502 352 olof
    RxOverrun <= 1'b0;
2503 354 olof
  else if(RxStatusWrite)
2504 352 olof
    RxOverrun <= 1'b0;
2505 354 olof
  else if(RxBufferFull & WriteRxDataToFifo_wb)
2506 352 olof
    RxOverrun <= 1'b1;
2507 60 mohor
end
2508 48 mohor
 
2509 77 mohor
 
2510
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2511
 
2512
 
2513 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2514 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2515 354 olof
// AddressMiss is identifying that a frame was received because of the
2516
// promiscous mode and is not an error
2517 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2518
 
2519 272 tadejm
 
2520 354 olof
// Latching and synchronizing RxStatusWrite signal. This signal is used for
2521
// clearing the ReceivedPauseFrm signal
2522 272 tadejm
always @ (posedge WB_CLK_I or posedge Reset)
2523
begin
2524
  if(Reset)
2525 352 olof
    RxStatusWriteLatched <= 1'b0;
2526 272 tadejm
  else
2527
  if(RxStatusWriteLatched_syncb2)
2528 352 olof
    RxStatusWriteLatched <= 1'b0;
2529 272 tadejm
  else
2530
  if(RxStatusWrite)
2531 352 olof
    RxStatusWriteLatched <= 1'b1;
2532 272 tadejm
end
2533
 
2534
 
2535
always @ (posedge MRxClk or posedge Reset)
2536
begin
2537
  if(Reset)
2538
    begin
2539 352 olof
      RxStatusWriteLatched_sync1 <= 1'b0;
2540
      RxStatusWriteLatched_sync2 <= 1'b0;
2541 272 tadejm
    end
2542
  else
2543
    begin
2544 352 olof
      RxStatusWriteLatched_sync1 <= RxStatusWriteLatched;
2545
      RxStatusWriteLatched_sync2 <= RxStatusWriteLatched_sync1;
2546 272 tadejm
    end
2547
end
2548
 
2549
 
2550
always @ (posedge WB_CLK_I or posedge Reset)
2551
begin
2552
  if(Reset)
2553
    begin
2554 352 olof
      RxStatusWriteLatched_syncb1 <= 1'b0;
2555
      RxStatusWriteLatched_syncb2 <= 1'b0;