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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_txethmac.v                                              ////
4 72 mohor
///                                                              ////
5 15 mohor
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////                                                              ////
13
////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
19
////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46 328 igorm
// Revision 1.8  2003/01/30 13:33:24  mohor
47
// When padding was enabled and crc disabled, frame was not ended correctly.
48
//
49 277 mohor
// Revision 1.7  2002/02/26 16:24:01  mohor
50
// RetryCntLatched was unused and removed from design
51
//
52 79 mohor
// Revision 1.6  2002/02/22 12:56:35  mohor
53
// Retry is not activated when a Tx Underrun occured
54
//
55 72 mohor
// Revision 1.5  2002/02/11 09:18:22  mohor
56
// Tx status is written back to the BD.
57
//
58 43 mohor
// Revision 1.4  2002/01/23 10:28:16  mohor
59
// Link in the header changed.
60
//
61 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
62
// eth_timescale.v changed to timescale.v This is done because of the
63
// simulation of the few cores in a one joined project.
64
//
65 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
66
// Few little NCSIM warnings fixed.
67
//
68 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
69
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
70
// Include files fixed to contain no path.
71
// File names and module names changed ta have a eth_ prologue in the name.
72
// File eth_timescale.v is used to define timescale
73
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
74
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
75
// and Mdo_OE. The bidirectional signal must be created on the top level. This
76
// is done due to the ASIC tools.
77
//
78 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
79
// Directory structure changed. Files checked and joind together.
80
//
81
// Revision 1.3  2001/06/19 18:16:40  mohor
82
// TxClk changed to MTxClk (as discribed in the documentation).
83
// Crc changed so only one file can be used instead of two.
84
//
85
// Revision 1.2  2001/06/19 10:38:08  mohor
86
// Minor changes in header.
87
//
88
// Revision 1.1  2001/06/19 10:27:58  mohor
89
// TxEthMAC initial release.
90
//
91
//
92
//
93
 
94 22 mohor
`include "timescale.v"
95 15 mohor
 
96
 
97
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
98
                     Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
99
                     IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
100
                     MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
101 43 mohor
                     ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
102 277 mohor
                     LateCollision, DeferIndication, StatePreamble, StateData
103 43 mohor
 
104 15 mohor
                    );
105
 
106
parameter Tp = 1;
107
 
108
 
109
input MTxClk;                   // Transmit clock (from PHY)
110
input Reset;                    // Reset
111
input TxStartFrm;               // Transmit packet start frame
112
input TxEndFrm;                 // Transmit packet end frame
113
input TxUnderRun;               // Transmit packet under-run
114
input [7:0] TxData;             // Transmit packet data byte
115
input CarrierSense;             // Carrier sense (synchronized)
116
input Collision;                // Collision (synchronized)
117
input Pad;                      // Pad enable (from register)
118
input CrcEn;                    // Crc enable (from register)
119
input FullD;                    // Full duplex (from register)
120
input HugEn;                    // Huge packets enable (from register)
121
input DlyCrcEn;                 // Delayed Crc enabled (from register)
122
input [15:0] MinFL;             // Minimum frame length (from register)
123
input [15:0] MaxFL;             // Maximum frame length (from register)
124
input [6:0] IPGT;               // Back to back transmit inter packet gap parameter (from register)
125
input [6:0] IPGR1;              // Non back to back transmit inter packet gap parameter IPGR1 (from register)
126
input [6:0] IPGR2;              // Non back to back transmit inter packet gap parameter IPGR2 (from register)
127
input [5:0] CollValid;          // Valid collision window (from register)
128
input [3:0] MaxRet;             // Maximum retry number (from register)
129
input NoBckof;                  // No backoff (from register)
130
input ExDfrEn;                  // Excessive defferal enable (from register)
131
 
132
output [3:0] MTxD;              // Transmit nibble (to PHY)
133
output MTxEn;                   // Transmit enable (to PHY)
134
output MTxErr;                  // Transmit error (to PHY)
135
output TxDone;                  // Transmit packet done (to RISC)
136
output TxRetry;                 // Transmit packet retry (to RISC)
137
output TxAbort;                 // Transmit packet abort (to RISC)
138
output TxUsedData;              // Transmit packet used data (to RISC)
139
output WillTransmit;            // Will transmit (to RxEthMAC)
140
output ResetCollision;          // Reset Collision (for synchronizing collision)
141 43 mohor
output [3:0] RetryCnt;          // Latched Retry Counter for tx status purposes
142
output StartTxDone;
143
output StartTxAbort;
144
output MaxCollisionOccured;
145
output LateCollision;
146 277 mohor
output DeferIndication;
147 43 mohor
output StatePreamble;
148
output [1:0] StateData;
149 15 mohor
 
150
reg [3:0] MTxD;
151
reg MTxEn;
152
reg MTxErr;
153
reg TxDone;
154
reg TxRetry;
155
reg TxAbort;
156
reg TxUsedData;
157
reg WillTransmit;
158
reg ColWindow;
159
reg StopExcessiveDeferOccured;
160
reg [3:0] RetryCnt;
161
reg [3:0] MTxD_d;
162
reg StatusLatch;
163
reg PacketFinished_q;
164
reg PacketFinished;
165
 
166
 
167
wire ExcessiveDeferOccured;
168
wire StartIPG;
169
wire StartPreamble;
170
wire [1:0] StartData;
171
wire StartFCS;
172
wire StartJam;
173 277 mohor
wire StartDefer;
174 15 mohor
wire StartBackoff;
175
wire StateDefer;
176
wire StateIPG;
177
wire StateIdle;
178
wire StatePAD;
179
wire StateFCS;
180
wire StateJam;
181 328 igorm
wire StateJam_q;
182 15 mohor
wire StateBackOff;
183
wire StateSFD;
184
wire StartTxRetry;
185
wire UnderRun;
186
wire TooBig;
187
wire [31:0] Crc;
188
wire CrcError;
189
wire [2:0] DlyCrcCnt;
190
wire [15:0] NibCnt;
191
wire NibCntEq7;
192
wire NibCntEq15;
193
wire NibbleMinFl;
194
wire ExcessiveDefer;
195
wire [15:0] ByteCnt;
196
wire MaxFrame;
197
wire RetryMax;
198
wire RandomEq0;
199
wire RandomEqByteCnt;
200
wire PacketFinished_d;
201
 
202
 
203
 
204 18 mohor
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
205 15 mohor
 
206
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
207
 
208 277 mohor
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
209 15 mohor
 
210
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
211
 
212
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
213
 
214 72 mohor
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
215
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
216 15 mohor
 
217
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
218
 
219
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
220
 
221
assign StateSFD = StatePreamble & NibCntEq15;
222
 
223
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
224
 
225
 
226
// StopExcessiveDeferOccured
227
always @ (posedge MTxClk or posedge Reset)
228
begin
229
  if(Reset)
230
    StopExcessiveDeferOccured <= #Tp 1'b0;
231
  else
232
    begin
233
      if(~TxStartFrm)
234
        StopExcessiveDeferOccured <= #Tp 1'b0;
235
      else
236
      if(ExcessiveDeferOccured)
237
        StopExcessiveDeferOccured <= #Tp 1'b1;
238
    end
239
end
240
 
241
 
242
// Collision Window
243
always @ (posedge MTxClk or posedge Reset)
244
begin
245
  if(Reset)
246
    ColWindow <= #Tp 1'b1;
247
  else
248
    begin
249
      if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
250
        ColWindow <= #Tp 1'b0;
251
      else
252
      if(StateIdle | StateIPG)
253
        ColWindow <= #Tp 1'b1;
254
    end
255
end
256
 
257
 
258
// Start Window
259
always @ (posedge MTxClk or posedge Reset)
260
begin
261
  if(Reset)
262
    StatusLatch <= #Tp 1'b0;
263
  else
264
    begin
265
      if(~TxStartFrm)
266
        StatusLatch <= #Tp 1'b0;
267
      else
268
      if(ExcessiveDeferOccured | StateIdle)
269
        StatusLatch <= #Tp 1'b1;
270
     end
271
end
272
 
273
 
274
// Transmit packet used data
275
always @ (posedge MTxClk or posedge Reset)
276
begin
277
  if(Reset)
278
    TxUsedData <= #Tp 1'b0;
279
  else
280
    TxUsedData <= #Tp |StartData;
281
end
282
 
283
 
284
// Transmit packet done
285
always @ (posedge MTxClk or posedge Reset)
286
begin
287
  if(Reset)
288
    TxDone <= #Tp 1'b0;
289
  else
290
    begin
291
      if(TxStartFrm & ~StatusLatch)
292
        TxDone <= #Tp 1'b0;
293
      else
294
      if(StartTxDone)
295
        TxDone <= #Tp 1'b1;
296
    end
297
end
298
 
299
 
300
// Transmit packet retry
301
always @ (posedge MTxClk or posedge Reset)
302
begin
303
  if(Reset)
304
    TxRetry <= #Tp 1'b0;
305
  else
306
    begin
307
      if(TxStartFrm & ~StatusLatch)
308
        TxRetry <= #Tp 1'b0;
309
      else
310
      if(StartTxRetry)
311
        TxRetry <= #Tp 1'b1;
312
     end
313
end
314
 
315
 
316
// Transmit packet abort
317
always @ (posedge MTxClk or posedge Reset)
318
begin
319
  if(Reset)
320
    TxAbort <= #Tp 1'b0;
321
  else
322
    begin
323
      if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
324
        TxAbort <= #Tp 1'b0;
325
      else
326
      if(StartTxAbort)
327
        TxAbort <= #Tp 1'b1;
328
    end
329
end
330
 
331
 
332
// Retry counter
333
always @ (posedge MTxClk or posedge Reset)
334
begin
335
  if(Reset)
336
    RetryCnt[3:0] <= #Tp 4'h0;
337
  else
338
    begin
339
      if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
340
          | StateJam & NibCntEq7 & (~ColWindow | RetryMax))
341
        RetryCnt[3:0] <= #Tp 4'h0;
342
      else
343
      if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
344
        RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
345
    end
346
end
347
 
348
 
349
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
350
 
351
 
352
// Transmit nibble
353
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
354 328 igorm
          Crc or NibCntEq15)
355 15 mohor
begin
356
  if(StateData[0])
357
    MTxD_d[3:0] = TxData[3:0];                                  // Lower nibble
358
  else
359
  if(StateData[1])
360
    MTxD_d[3:0] = TxData[7:4];                                  // Higher nibble
361
  else
362
  if(StateFCS)
363
    MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]};     // Crc
364
  else
365
  if(StateJam)
366
    MTxD_d[3:0] = 4'h9;                                         // Jam pattern
367
  else
368
  if(StatePreamble)
369
    if(NibCntEq15)
370
      MTxD_d[3:0] = 4'hd;                                       // SFD
371
    else
372
      MTxD_d[3:0] = 4'h5;                                       // Preamble
373
  else
374
    MTxD_d[3:0] = 4'h0;
375
end
376
 
377
 
378
// Transmit Enable
379
always @ (posedge MTxClk or posedge Reset)
380
begin
381
  if(Reset)
382
    MTxEn <= #Tp 1'b0;
383
  else
384 18 mohor
    MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
385 15 mohor
end
386
 
387
 
388
// Transmit nibble
389
always @ (posedge MTxClk or posedge Reset)
390
begin
391
  if(Reset)
392
    MTxD[3:0] <= #Tp 4'h0;
393
  else
394
    MTxD[3:0] <= #Tp MTxD_d[3:0];
395
end
396
 
397
 
398
// Transmit error
399
always @ (posedge MTxClk or posedge Reset)
400
begin
401
  if(Reset)
402
    MTxErr <= #Tp 1'b0;
403
  else
404
    MTxErr <= #Tp TooBig | UnderRun;
405
end
406
 
407
 
408
// WillTransmit
409
always @ (posedge MTxClk or posedge Reset)
410
begin
411
  if(Reset)
412
    WillTransmit <= #Tp  1'b0;
413
  else
414 18 mohor
    WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
415 15 mohor
end
416
 
417
 
418
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
419
 
420
 
421
// Packet finished
422
always @ (posedge MTxClk or posedge Reset)
423
begin
424
  if(Reset)
425
    begin
426
      PacketFinished <= #Tp 1'b0;
427
      PacketFinished_q  <= #Tp 1'b0;
428
    end
429
  else
430
    begin
431
      PacketFinished <= #Tp PacketFinished_d;
432
      PacketFinished_q  <= #Tp PacketFinished;
433
    end
434
end
435
 
436
 
437
// Connecting module Counters
438 349 olof
eth_txcounters #(.Tp(Tp))
439
txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
440 15 mohor
                            .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
441
                            .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
442
                            .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
443
                            .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
444
                            .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
445
                            .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
446
                            .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
447
                            .DlyCrcCnt(DlyCrcCnt)
448
                           );
449
 
450
 
451
// Connecting module StateM
452 349 olof
eth_txstatem #(.Tp(Tp))
453
txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
454 15 mohor
                        .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
455
                        .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
456
                        .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
457
                        .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
458
                        .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
459
                        .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
460
                        .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
461
                        .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
462
                        .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
463 277 mohor
                        .StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
464 15 mohor
                       );
465
 
466
 
467
wire Enable_Crc;
468
wire [3:0] Data_Crc;
469
wire Initialize_Crc;
470
 
471
assign Enable_Crc = ~StateFCS;
472
 
473
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
474
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
475
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
476
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
477
 
478 18 mohor
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
479 15 mohor
 
480
 
481
// Connecting module Crc
482 349 olof
eth_crc #(.Tp(Tp))
483
txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
484 15 mohor
               .Crc(Crc), .CrcError(CrcError)
485
              );
486
 
487
 
488
// Connecting module Random
489 349 olof
eth_random #(.Tp(Tp))
490
random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
491 15 mohor
                    .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
492
 
493
 
494
 
495
 
496
endmodule

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