OpenCores

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_fifo.v] - Blame information for rev 356

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 40 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_fifo.v                                                  ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 40 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 330 igorm
// Revision 1.3  2002/04/22 13:45:52  mohor
45
// Generic ram or Xilinx ram can be used in fifo (selectable by setting
46
// ETH_FIFO_XILINX in eth_defines.v).
47
//
48 100 mohor
// Revision 1.2  2002/03/25 13:33:04  mohor
49
// When clear and read/write are active at the same time, cnt and pointers are
50
// set to 1.
51
//
52 94 mohor
// Revision 1.1  2002/02/05 16:44:39  mohor
53
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
54
// MHz. Statuses, overrun, control frame transmission and reception still  need
55
// to be fixed.
56 40 mohor
//
57 94 mohor
//
58 40 mohor
 
59 356 olof
`include "ethmac_defines.v"
60 40 mohor
`include "timescale.v"
61
 
62 354 olof
module eth_fifo (data_in, data_out, clk, reset, write, read, clear,
63
                 almost_full, full, almost_empty, empty, cnt);
64 40 mohor
 
65
parameter DATA_WIDTH    = 32;
66
parameter DEPTH         = 8;
67
parameter CNT_WIDTH     = 4;
68
 
69
input                     clk;
70
input                     reset;
71
input                     write;
72
input                     read;
73
input                     clear;
74
input   [DATA_WIDTH-1:0]  data_in;
75
 
76
output  [DATA_WIDTH-1:0]  data_out;
77
output                    almost_full;
78
output                    full;
79
output                    almost_empty;
80
output                    empty;
81 100 mohor
output  [CNT_WIDTH-1:0]   cnt;
82 40 mohor
 
83 100 mohor
`ifdef ETH_FIFO_XILINX
84
`else
85 330 igorm
  `ifdef ETH_ALTERA_ALTSYNCRAM
86
  `else
87
    reg     [DATA_WIDTH-1:0]  fifo  [0:DEPTH-1];
88
    reg     [DATA_WIDTH-1:0]  data_out;
89
  `endif
90 100 mohor
`endif
91
 
92 40 mohor
reg     [CNT_WIDTH-1:0]   cnt;
93
reg     [CNT_WIDTH-2:0]   read_pointer;
94
reg     [CNT_WIDTH-2:0]   write_pointer;
95
 
96
 
97
always @ (posedge clk or posedge reset)
98
begin
99
  if(reset)
100 352 olof
    cnt <= 0;
101 40 mohor
  else
102
  if(clear)
103 352 olof
    cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write};
104 40 mohor
  else
105
  if(read ^ write)
106
    if(read)
107 352 olof
      cnt <= cnt - 1'b1;
108 40 mohor
    else
109 352 olof
      cnt <= cnt + 1'b1;
110 40 mohor
end
111
 
112 354 olof
 
113 40 mohor
always @ (posedge clk or posedge reset)
114
begin
115
  if(reset)
116 352 olof
    read_pointer <= 0;
117 40 mohor
  else
118
  if(clear)
119 352 olof
    read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read};
120 40 mohor
  else
121
  if(read & ~empty)
122 352 olof
    read_pointer <= read_pointer + 1'b1;
123 40 mohor
end
124
 
125
always @ (posedge clk or posedge reset)
126
begin
127
  if(reset)
128 352 olof
    write_pointer <= 0;
129 40 mohor
  else
130
  if(clear)
131 352 olof
    write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write};
132 40 mohor
  else
133
  if(write & ~full)
134 352 olof
    write_pointer <= write_pointer + 1'b1;
135 40 mohor
end
136
 
137
assign empty = ~(|cnt);
138
assign almost_empty = cnt == 1;
139
assign full  = cnt == DEPTH;
140
assign almost_full  = &cnt[CNT_WIDTH-2:0];
141
 
142
 
143
 
144 100 mohor
`ifdef ETH_FIFO_XILINX
145
  xilinx_dist_ram_16x32 fifo
146
  ( .data_out(data_out),
147
    .we(write & ~full),
148
    .data_in(data_in),
149
    .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
150
    .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
151
    .wclk(clk)
152
  );
153 330 igorm
`else   // !ETH_FIFO_XILINX
154
`ifdef ETH_ALTERA_ALTSYNCRAM
155
  altera_dpram_16x32    altera_dpram_16x32_inst
156
  (
157
        .data             (data_in),
158
        .wren             (write & ~full),
159
        .wraddress        (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
160
        .rdaddress        (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
161
        .clock            (clk),
162
        .q                (data_out)
163
  );  //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
164
`else   // !ETH_ALTERA_ALTSYNCRAM
165 100 mohor
  always @ (posedge clk)
166
  begin
167
    if(write & clear)
168 352 olof
      fifo[0] <= data_in;
169 100 mohor
    else
170
   if(write & ~full)
171 352 olof
      fifo[write_pointer] <= data_in;
172 100 mohor
  end
173
 
174 40 mohor
 
175 330 igorm
  always @ (posedge clk)
176
  begin
177
    if(clear)
178 352 olof
      data_out <= fifo[0];
179 330 igorm
    else
180 352 olof
      data_out <= fifo[read_pointer];
181 330 igorm
  end
182
`endif  // !ETH_ALTERA_ALTSYNCRAM
183
`endif  // !ETH_FIFO_XILINX
184 100 mohor
 
185 330 igorm
 
186 40 mohor
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.