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1 129 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_cop.v                                                   ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 129 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
15
////                                                              ////
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//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
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////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
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////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 286 mohor
// Revision 1.3  2002/10/10 16:43:59  mohor
45
// Minor $display change.
46
//
47 212 mohor
// Revision 1.2  2002/09/09 12:54:13  mohor
48
// error acknowledge cycle termination added to display.
49
//
50 160 mohor
// Revision 1.1  2002/08/14 17:16:07  mohor
51
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
52
// interfaces:
53
// - Host connects to the master interface
54
// - Ethernet master (DMA) connects to the second master interface
55
// - Memory interface connects to the slave interface
56
// - Ethernet slave interface (access to registers and BDs) connects to second
57
//   slave interface
58 129 mohor
//
59
//
60
//
61
//
62 160 mohor
//
63 129 mohor
 
64
`include "timescale.v"
65
 
66
module eth_cop
67
(
68
  // WISHBONE common
69
  wb_clk_i, wb_rst_i,
70
 
71
  // WISHBONE MASTER 1
72
  m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i,  m1_wb_dat_o,
73
  m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
74
  m1_wb_err_o,
75
 
76
  // WISHBONE MASTER 2
77
  m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i,  m2_wb_dat_o,
78
  m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
79
  m2_wb_err_o,
80
 
81
  // WISHBONE slave 1
82
        s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o,  s1_wb_cyc_o,
83
        s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
84
        s1_wb_dat_o,
85
 
86
  // WISHBONE slave 2
87
        s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o,  s2_wb_cyc_o,
88
        s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
89
        s2_wb_dat_o
90
);
91
 
92
parameter Tp=1;
93 351 olof
parameter ETH_BASE     = 32'hd0000000;
94
parameter ETH_WIDTH    = 32'h800;
95
parameter MEMORY_BASE  = 32'h2000;
96
parameter MEMORY_WIDTH = 32'h10000;
97
 
98 129 mohor
// WISHBONE common
99
input wb_clk_i, wb_rst_i;
100
 
101
// WISHBONE MASTER 1
102
input  [31:0] m1_wb_adr_i, m1_wb_dat_i;
103
input   [3:0] m1_wb_sel_i;
104
input         m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
105
output [31:0] m1_wb_dat_o;
106
output        m1_wb_ack_o, m1_wb_err_o;
107
 
108
// WISHBONE MASTER 2
109
input  [31:0] m2_wb_adr_i, m2_wb_dat_i;
110
input   [3:0] m2_wb_sel_i;
111
input         m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
112
output [31:0] m2_wb_dat_o;
113
output        m2_wb_ack_o, m2_wb_err_o;
114
 
115
// WISHBONE slave 1
116
input  [31:0] s1_wb_dat_i;
117
input         s1_wb_ack_i, s1_wb_err_i;
118
output [31:0] s1_wb_adr_o, s1_wb_dat_o;
119
output  [3:0] s1_wb_sel_o;
120
output        s1_wb_we_o,  s1_wb_cyc_o, s1_wb_stb_o;
121
 
122
// WISHBONE slave 2
123
input  [31:0] s2_wb_dat_i;
124
input         s2_wb_ack_i, s2_wb_err_i;
125
output [31:0] s2_wb_adr_o, s2_wb_dat_o;
126
output  [3:0] s2_wb_sel_o;
127
output        s2_wb_we_o,  s2_wb_cyc_o, s2_wb_stb_o;
128
 
129
reg           m1_in_progress;
130
reg           m2_in_progress;
131
reg    [31:0] s1_wb_adr_o;
132
reg     [3:0] s1_wb_sel_o;
133
reg           s1_wb_we_o;
134
reg    [31:0] s1_wb_dat_o;
135
reg           s1_wb_cyc_o;
136
reg           s1_wb_stb_o;
137
reg    [31:0] s2_wb_adr_o;
138
reg     [3:0] s2_wb_sel_o;
139
reg           s2_wb_we_o;
140
reg    [31:0] s2_wb_dat_o;
141
reg           s2_wb_cyc_o;
142
reg           s2_wb_stb_o;
143
 
144
reg           m1_wb_ack_o;
145
reg    [31:0] m1_wb_dat_o;
146
reg           m2_wb_ack_o;
147
reg    [31:0] m2_wb_dat_o;
148
 
149
reg           m1_wb_err_o;
150
reg           m2_wb_err_o;
151
 
152
wire m_wb_access_finished;
153 351 olof
wire m1_addressed_s1 = (m1_wb_adr_i >= ETH_BASE) &
154
                       (m1_wb_adr_i < (ETH_BASE + ETH_WIDTH));
155
wire m1_addressed_s2 = (m1_wb_adr_i >= MEMORY_BASE) &
156
                       (m1_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH));
157
wire m2_addressed_s1 = (m2_wb_adr_i >= ETH_BASE) &
158
                       (m2_wb_adr_i < (ETH_BASE + ETH_WIDTH));
159
wire m2_addressed_s2 = (m2_wb_adr_i >= MEMORY_BASE) &
160
                       (m2_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH));
161 350 olof
 
162
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (m1_addressed_s1 | m1_addressed_s2);
163
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (m2_addressed_s1 | m2_addressed_s2);
164 129 mohor
 
165
always @ (posedge wb_clk_i or posedge wb_rst_i)
166
begin
167
  if(wb_rst_i)
168
    begin
169
      m1_in_progress <=#Tp 0;
170
      m2_in_progress <=#Tp 0;
171
      s1_wb_adr_o    <=#Tp 0;
172
      s1_wb_sel_o    <=#Tp 0;
173
      s1_wb_we_o     <=#Tp 0;
174
      s1_wb_dat_o    <=#Tp 0;
175
      s1_wb_cyc_o    <=#Tp 0;
176
      s1_wb_stb_o    <=#Tp 0;
177
      s2_wb_adr_o    <=#Tp 0;
178
      s2_wb_sel_o    <=#Tp 0;
179
      s2_wb_we_o     <=#Tp 0;
180
      s2_wb_dat_o    <=#Tp 0;
181
      s2_wb_cyc_o    <=#Tp 0;
182
      s2_wb_stb_o    <=#Tp 0;
183
    end
184
  else
185
    begin
186
      case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished})  // synopsys_full_case synopsys_paralel_case
187
        5'b00_10_0, 5'b00_11_0 :
188
          begin
189
            m1_in_progress <=#Tp 1'b1;  // idle: m1 or (m1 & m2) want access: m1 -> m
190 350 olof
            if(m1_addressed_s1)
191 129 mohor
              begin
192
                s1_wb_adr_o <=#Tp m1_wb_adr_i;
193
                s1_wb_sel_o <=#Tp m1_wb_sel_i;
194
                s1_wb_we_o  <=#Tp m1_wb_we_i;
195
                s1_wb_dat_o <=#Tp m1_wb_dat_i;
196
                s1_wb_cyc_o <=#Tp 1'b1;
197
                s1_wb_stb_o <=#Tp 1'b1;
198
              end
199 350 olof
            else if(m1_addressed_s2)
200 129 mohor
              begin
201
                s2_wb_adr_o <=#Tp m1_wb_adr_i;
202
                s2_wb_sel_o <=#Tp m1_wb_sel_i;
203
                s2_wb_we_o  <=#Tp m1_wb_we_i;
204
                s2_wb_dat_o <=#Tp m1_wb_dat_i;
205
                s2_wb_cyc_o <=#Tp 1'b1;
206
                s2_wb_stb_o <=#Tp 1'b1;
207
              end
208
            else
209
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
210
          end
211
        5'b00_01_0 :
212
          begin
213
            m2_in_progress <=#Tp 1'b1;  // idle: m2 wants access: m2 -> m
214 350 olof
            if(m2_addressed_s1)
215 129 mohor
              begin
216
                s1_wb_adr_o <=#Tp m2_wb_adr_i;
217
                s1_wb_sel_o <=#Tp m2_wb_sel_i;
218
                s1_wb_we_o  <=#Tp m2_wb_we_i;
219
                s1_wb_dat_o <=#Tp m2_wb_dat_i;
220
                s1_wb_cyc_o <=#Tp 1'b1;
221
                s1_wb_stb_o <=#Tp 1'b1;
222
              end
223 350 olof
            else if(m2_addressed_s2)
224 129 mohor
              begin
225
                s2_wb_adr_o <=#Tp m2_wb_adr_i;
226
                s2_wb_sel_o <=#Tp m2_wb_sel_i;
227
                s2_wb_we_o  <=#Tp m2_wb_we_i;
228
                s2_wb_dat_o <=#Tp m2_wb_dat_i;
229
                s2_wb_cyc_o <=#Tp 1'b1;
230
                s2_wb_stb_o <=#Tp 1'b1;
231
              end
232
            else
233
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
234
          end
235
        5'b10_10_1, 5'b10_11_1 :
236
          begin
237
            m1_in_progress <=#Tp 1'b0;  // m1 in progress. Cycle is finished. Send ack or err to m1.
238 350 olof
            if(m1_addressed_s1)
239 129 mohor
              begin
240
                s1_wb_cyc_o <=#Tp 1'b0;
241
                s1_wb_stb_o <=#Tp 1'b0;
242
              end
243 350 olof
            else if(m1_addressed_s2)
244 129 mohor
              begin
245
                s2_wb_cyc_o <=#Tp 1'b0;
246
                s2_wb_stb_o <=#Tp 1'b0;
247
              end
248
          end
249
        5'b01_01_1, 5'b01_11_1 :
250
          begin
251
            m2_in_progress <=#Tp 1'b0;  // m2 in progress. Cycle is finished. Send ack or err to m2.
252 350 olof
            if(m2_addressed_s1)
253 129 mohor
              begin
254
                s1_wb_cyc_o <=#Tp 1'b0;
255
                s1_wb_stb_o <=#Tp 1'b0;
256
              end
257 350 olof
            else if(m2_addressed_s2)
258 129 mohor
              begin
259
                s2_wb_cyc_o <=#Tp 1'b0;
260
                s2_wb_stb_o <=#Tp 1'b0;
261
              end
262
          end
263
      endcase
264
    end
265
end
266
 
267
// Generating Ack for master 1
268 350 olof
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or m1_addressed_s1 or m1_addressed_s2)
269 129 mohor
begin
270
  if(m1_in_progress)
271
    begin
272 350 olof
      if(m1_addressed_s1) begin
273 129 mohor
        m1_wb_ack_o <= s1_wb_ack_i;
274
        m1_wb_dat_o <= s1_wb_dat_i;
275
      end
276 350 olof
      else if(m1_addressed_s2) begin
277 129 mohor
        m1_wb_ack_o <= s2_wb_ack_i;
278
        m1_wb_dat_o <= s2_wb_dat_i;
279
      end
280
    end
281
  else
282
    m1_wb_ack_o <= 0;
283
end
284
 
285
 
286
// Generating Ack for master 2
287 350 olof
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or m2_addressed_s1 or m2_addressed_s2)
288 129 mohor
begin
289
  if(m2_in_progress)
290
    begin
291 350 olof
      if(m2_addressed_s1) begin
292 129 mohor
        m2_wb_ack_o <= s1_wb_ack_i;
293
        m2_wb_dat_o <= s1_wb_dat_i;
294
      end
295 350 olof
      else if(m2_addressed_s2) begin
296 129 mohor
        m2_wb_ack_o <= s2_wb_ack_i;
297
        m2_wb_dat_o <= s2_wb_dat_i;
298
      end
299
    end
300
  else
301
    m2_wb_ack_o <= 0;
302
end
303
 
304
 
305
// Generating Err for master 1
306 350 olof
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or m2_addressed_s1 or m2_addressed_s2 or
307 129 mohor
          m1_wb_cyc_i or m1_wb_stb_i)
308
begin
309
  if(m1_in_progress)  begin
310 350 olof
    if(m1_addressed_s1)
311 129 mohor
      m1_wb_err_o <= s1_wb_err_i;
312 350 olof
    else if(m1_addressed_s2)
313 129 mohor
      m1_wb_err_o <= s2_wb_err_i;
314
  end
315 350 olof
  else if(m1_wb_cyc_i & m1_wb_stb_i & ~m1_addressed_s1 & ~m1_addressed_s2)
316 129 mohor
    m1_wb_err_o <= 1'b1;
317
  else
318
    m1_wb_err_o <= 1'b0;
319
end
320
 
321
 
322
// Generating Err for master 2
323 350 olof
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or m2_addressed_s1 or m2_addressed_s2 or
324 129 mohor
          m2_wb_cyc_i or m2_wb_stb_i)
325
begin
326
  if(m2_in_progress)  begin
327 350 olof
    if(m2_addressed_s1)
328 129 mohor
      m2_wb_err_o <= s1_wb_err_i;
329 350 olof
    else if(m2_addressed_s2)
330 129 mohor
      m2_wb_err_o <= s2_wb_err_i;
331
  end
332 350 olof
  else if(m2_wb_cyc_i & m2_wb_stb_i & ~m2_addressed_s1 & ~m2_addressed_s2)
333 129 mohor
    m2_wb_err_o <= 1'b1;
334
  else
335
    m2_wb_err_o <= 1'b0;
336
end
337
 
338
 
339
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
340
 
341
 
342
// Activity monitor
343
integer cnt;
344
always @ (posedge wb_clk_i or posedge wb_rst_i)
345
begin
346
  if(wb_rst_i)
347
    cnt <=#Tp 0;
348
  else
349
  if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
350
    cnt <=#Tp 0;
351
  else
352
  if(s1_wb_cyc_o | s2_wb_cyc_o)
353
    cnt <=#Tp cnt+1;
354
end
355
 
356
always @ (posedge wb_clk_i)
357
begin
358
  if(cnt==1000) begin
359 212 mohor
    $display("(%0t)(%m) ERROR: WB activity ??? ", $time);
360 129 mohor
    if(s1_wb_cyc_o) begin
361
      $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
362
      $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
363
      $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
364
      $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
365
    end
366 160 mohor
    else if(s2_wb_cyc_o) begin
367 129 mohor
      $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
368
      $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
369
      $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
370
      $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
371
    end
372
 
373
    $stop;
374
  end
375
end
376
 
377
 
378 160 mohor
always @ (posedge wb_clk_i)
379
begin
380
  if(s1_wb_err_i & s1_wb_cyc_o) begin
381
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
382
    $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
383
    $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
384
    $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
385
    $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
386
    $stop;
387
  end
388
  if(s2_wb_err_i & s2_wb_cyc_o) begin
389
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
390
    $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
391
    $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
392
    $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
393
    $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
394
    $stop;
395
  end
396
end
397 129 mohor
 
398 160 mohor
 
399
 
400 286 mohor
endmodule

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